Intel® Atom™ Processor E3800
Product Family
Datasheet
January 2015
Revision 3.6
Reference Number: 538136
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2
Intel® Atom™ Processor E3800 Product Family
Datasheet
Contents
1
Introduction ............................................................................................................ 27
1.1
1.2
2
Physical Interfaces .................................................................................................. 36
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
2.23
2.24
2.25
2.26
2.27
2.28
2.29
2.30
2.31
3
Pin States Through Reset ................................................................................... 38
System Memory Controller Interface Signals ......................................................... 39
PCI Express* 2.0 Interface Signals ...................................................................... 41
USB 2.0 Host (EHCI/xHCI) Interface Signals ......................................................... 41
USB 2.0 HSIC Interface Signals........................................................................... 42
USB 3.0 (xHCI) Host Interface Signals ................................................................. 42
USB 2.0 Device (ULPI) Interface Signals............................................................... 42
USB 3.0 Device Interface Signals......................................................................... 43
Serial ATA (SATA) 2.0 Interface Signals ............................................................... 44
Integrated Clock Interface Signals ....................................................................... 44
Display - Digital Display Interface (DDI) Signals .................................................... 45
Display – VGA Interface Signals .......................................................................... 46
MIPI Camera Serial Interface (CSI) and ISP Interface Signals.................................. 46
Intel® High Definition Audio Interface Signals ....................................................... 47
Low Power Engine (LPE) for Audio (I2S) Interface Signals ....................................... 47
Storage Control Cluster (eMMC, SDIO, SD) Interface Signals................................... 48
SIO – High Speed UART Interface Signals ............................................................. 49
SIO – I2C Interface Signals................................................................................. 50
SIO – Serial Peripheral Interface (SPI) Signals ...................................................... 50
PCU – iLB – Real Time Clock (RTC) Interface Signals .............................................. 51
PCU – iLB – Low Pin Count (LPC) Bridge Interface Signals ....................................... 51
PCU – Serial Peripheral Interface (SPI) Signals ...................................................... 52
PCU – System Management Bus (SMBus) Interface Signals ..................................... 53
PCU – Power Management Controller (PMC) Interface Signals.................................. 53
JTAG and Debug Interface Signals ....................................................................... 54
Miscellaneous Signals ........................................................................................ 54
GPIO Signals .................................................................................................... 55
Power And Ground Pins ...................................................................................... 59
Hardware Straps ............................................................................................... 61
Configurable IO: GPIO Muxing ............................................................................ 62
Reserved Pins ................................................................................................... 62
Register Access Methods ......................................................................................... 63
3.1
3.2
3.3
3.4
3.5
3.6
3.7
4
Terminology ..................................................................................................... 29
Feature Overview .............................................................................................. 30
Fixed IO Register Access .................................................................................... 63
Fixed Memory Mapped Register Access................................................................. 63
IO Referenced Register Access ............................................................................ 63
Memory Referenced Register Access .................................................................... 64
PCI Configuration Register Access........................................................................ 64
Message Bus Register Access .............................................................................. 66
Register Field Access Types ................................................................................ 67
Mapping Address Spaces ......................................................................................... 69
4.1
4.2
Physical Address Space Mappings ........................................................................ 69
IO Address Space.............................................................................................. 75
Intel® Atom™ Processor E3800 Product Family
Datasheet
3
4.3
5
Integrated Clock ......................................................................................................79
5.1
6
Signal Descriptions .......................................................................................... 274
Features ......................................................................................................... 278
System Memory Controller (D-Unit) Message Registers ......................................... 281
SoC Transaction Router.......................................................................................... 316
13.1
13.2
13.3
13.4
4
Features ......................................................................................................... 269
Platform Identification and CPUID ...................................................................... 272
References...................................................................................................... 273
System Memory Controller ..................................................................................... 274
12.1
12.2
12.3
13
SoC Attributes................................................................................................. 207
Package Diagrams ........................................................................................... 208
Ball Name and Function by Location ................................................................... 210
Alphabetical Ball Name List ............................................................................... 258
Processor Core....................................................................................................... 269
11.1
11.2
11.3
12
Thermal Specifications...................................................................................... 111
Storage Conditions........................................................................................... 112
Voltage and Current Specifications ..................................................................... 113
Crystal Specifications ....................................................................................... 123
DC Specifications ............................................................................................. 124
AC Specifications ............................................................................................. 146
Ballout and Package Information ........................................................................... 207
10.1
10.2
10.3
10.4
11
CPU Thermal Management Registers ................................................................. 108
Thermal Sensors.............................................................................................. 108
SoC Programmable Trips .................................................................................. 109
Platform Trips ................................................................................................. 110
Thermal Throttling Mechanisms ......................................................................... 110
Thermal Status................................................................................................ 110
Electrical Specifications ......................................................................................... 111
9.1
9.2
9.3
9.4
9.5
9.6
10
SoC System States ............................................................................................97
Power Up Sequences ..........................................................................................97
Power Down Sequences .................................................................................... 102
Reset Behavior ................................................................................................ 105
Thermal Management ............................................................................................ 108
8.1
8.2
8.3
8.4
8.5
8.6
9
Power Management Features...............................................................................83
Power Management States Supported...................................................................83
Processor Core Power Management ......................................................................88
Memory Controller Power Management .................................................................94
PCI Express* (PCIe*) Power Management .............................................................96
Power Up and Reset Sequence .................................................................................97
7.1
7.2
7.3
7.4
8
Features ...........................................................................................................80
Power Management .................................................................................................83
6.1
6.2
6.3
6.4
6.5
7
PCI Configuration Space .....................................................................................76
Transaction Router A-Unit Message Registers ...................................................... 318
SoC Transaction Router PCI Config Access IO Registers ........................................ 321
Transaction Router B-Unit Message Registers ...................................................... 323
Transaction Router C-Unit PCI Registers ............................................................. 338
Intel® Atom™ Processor E3800 Product Family
Datasheet
13.5
13.6
14
Graphics, Video and Display .................................................................................. 405
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
14.10
14.11
14.12
14.13
15
Signal Descriptions .........................................................................................1037
Features .......................................................................................................1039
Imaging Subsystem Integration .......................................................................1042
Functional Description.....................................................................................1044
MIPI-CSI-2 Receiver .......................................................................................1046
Register Map .................................................................................................1048
Image Signal Processor PCI Configuration Registers ............................................1050
Image Signal Processor Memory Mapped IO Registers .........................................1076
Storage Control Cluster (eMMC, SDIO, SD Card) ...................................................1744
16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
16.9
16.10
17
Features ........................................................................................................ 405
SoC Graphics Display ....................................................................................... 406
Display Pipes .................................................................................................. 407
Display Physical Interfaces ............................................................................... 407
References ..................................................................................................... 413
3D Graphics and Video ..................................................................................... 413
Features ........................................................................................................ 414
VED (Video Encode/Decode) ............................................................................. 416
PCI Configuration Registers .............................................................................. 419
Memory Mapped Registers (1 of 2) .................................................................... 445
Memory Mapped Registers (2 of 2) .................................................................... 635
Memory Mapped Registers (Read Only) .............................................................1027
Memory Mapped Registers (Write Only).............................................................1033
MIPI-Camera Serial Interface (CSI) and ISP ........................................................1037
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
16
Transaction Router C-Unit Message Registers ...................................................... 345
Transaction Router P-Unit Message Registers ...................................................... 351
Signal Descriptions .........................................................................................1744
Features .......................................................................................................1746
References ....................................................................................................1748
Register Map .................................................................................................1749
SDIO for Wifi PCI Configuration Registers ..........................................................1751
SDIO for Wifi Memory Mapped IO Registers .......................................................1763
SD Card PCI Configuration Registers .................................................................1807
SD Card Memory Mapped IO Registers ..............................................................1819
eMMC 4.5 PCI Configuration Registers...............................................................1863
eMMC 4.5 Memory Mapped IO Registers ............................................................1875
Serial ATA (SATA).................................................................................................1919
17.1
17.2
17.3
17.4
17.5
17.6
17.7
17.8
17.9
17.10
17.11
17.12
17.13
Signal Descriptions .........................................................................................1919
Features .......................................................................................................1920
References ....................................................................................................1922
Register Map .................................................................................................1923
SATA PCI Configuration Registers .....................................................................1924
SATA Legacy IO Registers ...............................................................................1953
SATA Index Pair IO Registers ...........................................................................1959
SATA AHCI Memory Mapped IO Registers ..........................................................1961
SATA Primary Read Command IO Registers .......................................................1998
SATA Primary Write Command IO Registers .......................................................2003
SATA Primary Read Control IO Registers ...........................................................2005
SATA Primary Write Control IO Registers ...........................................................2006
SATA Secondary Read Command IO Registers....................................................2007
Intel® Atom™ Processor E3800 Product Family
Datasheet
5
17.14
17.15
17.16
17.17
17.18
17.19
17.20
18
Signal Descriptions ........................................................................................ 2663
Features ....................................................................................................... 2664
References.................................................................................................... 2664
Register Map................................................................................................. 2665
HD Audio PCI Configuration Registers ............................................................... 2667
HD Audio Memory Mapped I/O Registers ........................................................... 2698
Low Power Engine (LPE) for Audio (I2S) .............................................................. 2798
21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8
21.9
21.10
21.11
21.12
21.13
21.14
21.15
21.16
6
USB Device Controller .................................................................................... 2445
References.................................................................................................... 2446
Register Map................................................................................................. 2446
USB 3.0 Device PCI Configuration Registers ...................................................... 2447
USB 3.0 Device PCI Configuration Registers ...................................................... 2456
USB 3.0 Device Memory Mapped I/O Registers .................................................. 2461
USB 3.0 Device Memory Mapped I/O Registers .................................................. 2642
Intel® High Definition Audio ................................................................................ 2662
20.1
20.2
20.3
20.4
20.5
20.6
21
Signal Descriptions ........................................................................................ 2112
USB 3.0 xHCI (Extensible Host Controller Interface) ........................................... 2114
USB 2.0 Enhanced Host Controller Interface (EHCI)............................................ 2115
References.................................................................................................... 2116
Register Map................................................................................................. 2117
USB xHCI PCI Configuration Registers .............................................................. 2120
USB xHCI Memory Mapped I/O Registers .......................................................... 2163
USB EHCI PCI Configuration Registers .............................................................. 2345
USB EHCI Memory Mapped IO Registers ........................................................... 2369
USB EHCI Electrical Message Bus Registers ....................................................... 2427
USB Device Controller Interfaces (3.0, ULPI) ....................................................... 2443
19.1
19.2
19.3
19.4
19.5
19.6
19.7
20
Secondary Write Command IO Registers................................................... 2012
Secondary Read Control IO Registers ....................................................... 2014
Secondary Write Control IO Registers....................................................... 2015
Lane 0 Electrical Register Address Map ..................................................... 2017
Lane 0 Electrical Register Address Map ..................................................... 2047
Lane 1 Electrical Register Address Map ..................................................... 2065
Lane 1 Electrical Register Address Map ..................................................... 2095
USB Host Controller Interfaces (xHCI, EHCI) ....................................................... 2112
18.1
18.2
18.3
18.4
18.5
18.6
18.7
18.8
18.9
18.10
19
SATA
SATA
SATA
SATA
SATA
SATA
SATA
Signal Descriptions ........................................................................................ 2798
Features ....................................................................................................... 2799
Detailed Block Level Description ...................................................................... 2800
Software Implementation Considerations .......................................................... 2803
Clocks .......................................................................................................... 2805
SSP (I2S) ..................................................................................................... 2808
Programming Model ....................................................................................... 2813
Register Map................................................................................................. 2818
Low Power Audio PCI Configuration Registers .................................................... 2819
pci_mem Address Map.................................................................................... 2827
Memory Mapped Shim Registers ...................................................................... 2837
Low Power Audio I2S0 Address Map.................................................................. 2864
Low Power Audio I2S0 Address Map.................................................................. 2884
Low Power Audio I2S0 Address Map.................................................................. 2904
Low Power Audio DMA0 Memory Mapped IO Registers ........................................ 2924
Low Power Audio DMA1 Memory Mapped IO Registers ........................................ 3037
Intel® Atom™ Processor E3800 Product Family
Datasheet
22
Intel® Trusted Execution Engine (TXE) .................................................................3150
22.1
22.2
22.3
23
PCI Express* 2.0 ..................................................................................................3179
23.1
23.2
23.3
23.4
23.5
23.6
23.7
23.8
23.9
23.10
23.11
23.12
23.13
23.14
24
Serial I/O (SIO) Register Map .........................................................................3420
SIO DMA PCI Configuration Registers for SPI, HSUART, PWM ...............................3421
SIO DMA Memory Mapped I/O Registers for SPI, HSUART, PWM ...........................3430
SIO DMA PCI Configuration Registers for I2C......................................................3604
SIO DMA Memory Mapped I/O Registers for I2C..................................................3613
SIO – Serial Peripheral Interface (SPI) ................................................................3788
25.1
25.2
25.3
25.4
25.5
26
Signal Descriptions .........................................................................................3179
Features .......................................................................................................3180
References ....................................................................................................3183
Register Map .................................................................................................3183
PCI Configuration Registers .............................................................................3185
PCI Express* PCI Configuration Registers ..........................................................3186
PCI Express* Lane 0 Electrical Address Map .......................................................3229
PCI Express* Lane 0 Electrical Address Map .......................................................3259
PCI Express* Lane 1 Electrical Address Map .......................................................3277
PCI Express* Lane 1 Electrical Address Map .......................................................3307
PCI Express* Lane 2 Electrical Address Map .......................................................3325
PCI Express* Lane 2 Electrical Address Map .......................................................3355
PCI Express* Lane 3 Electrical Address Map .......................................................3373
PCI Express* Lane 3 Electrical Address Map .......................................................3403
Serial IO (SIO) Overview......................................................................................3420
24.1
24.2
24.3
24.4
24.5
25
Features .......................................................................................................3150
Register Map .................................................................................................3151
Intel® TXE PCI Configuration Registers..............................................................3153
Signal Descriptions .........................................................................................3788
Features .......................................................................................................3789
Register Map .................................................................................................3792
SIO SPI PCI Configuration Registers..................................................................3793
SIO SPI Memory Mapped I/O Registers .............................................................3802
SIO - I2C Interface ...............................................................................................3819
26.1
26.2
26.3
26.4
26.5
26.6
26.7
26.8
26.9
26.10
26.11
26.12
26.13
26.14
26.15
26.16
26.17
Signal Descriptions .........................................................................................3819
Features .......................................................................................................3820
Use ..............................................................................................................3826
References ....................................................................................................3828
Register Map .................................................................................................3828
SIO I2C 0 PCI Configuration Registers ...............................................................3830
SIO I2C 0 Memory Mapped I/O Registers ...........................................................3839
SIO I2C 1 PCI Configuration Registers ...............................................................3878
SIO I2C 1 PCI Configuration Registers ...............................................................3888
SIO I2C 2 PCI Configuration Registers ...............................................................3927
SIO I2C 2 Memory Mapped I/O Registers ...........................................................3937
SIO I2C 3 PCI Configuration Registers ...............................................................3976
SIO I2C 3 Memory Mapped I/O Registers ...........................................................3986
SIO I2C 4 PCI Configuration Registers ...............................................................4025
SIO I2C 4 Memory Mapped I/O Registers ...........................................................4035
SIO I2C 5 PCI Configuration Registers ...............................................................4074
SIO I2C 5 Memory Mapped I/O Registers ...........................................................4084
Intel® Atom™ Processor E3800 Product Family
Datasheet
7
26.18 SIO I2C 6 PCI Configuration Registers .............................................................. 4123
26.19 SIO I2C 6 Memory Mapped I/O Registers .......................................................... 4133
27
SIO – High Speed UART ....................................................................................... 4172
27.1
27.2
27.3
27.4
27.5
27.6
27.7
27.8
28
SIO – Pulse Width Modulation (PWM) .................................................................. 4262
28.1
28.2
28.3
28.4
28.5
28.6
28.7
28.8
29
Signal Descriptions ........................................................................................ 4415
Features ....................................................................................................... 4416
Use.............................................................................................................. 4418
UART Enable/Disable...................................................................................... 4418
IO Mapped Registers ...................................................................................... 4419
PCU iLB UART IO Registers.............................................................................. 4420
PCU – System Management Bus (SMBus) ............................................................. 4429
33.1
8
Signal Descriptions ........................................................................................ 4365
Features ....................................................................................................... 4366
Use.............................................................................................................. 4378
Register Map................................................................................................. 4380
PCU SPI for Firmware Memory Mapped I/O Registers .......................................... 4381
PCU – Universal Asynchronous Receiver/Transmitter (UART) .............................. 4415
32.1
32.2
32.3
32.4
32.5
32.6
33
Signal Descriptions ........................................................................................ 4299
Features ....................................................................................................... 4301
USB Per-Port Register Write Control ................................................................. 4310
References.................................................................................................... 4310
Register Map................................................................................................. 4310
PCU PMC Memory Mapped I/O Registers ........................................................... 4311
PCU PMC IO Registers .................................................................................... 4345
PCU iLB PMC I/O Registers .............................................................................. 4348
PCU – Serial Peripheral Interface (SPI) ............................................................... 4365
31.1
31.2
31.3
31.4
31.5
32
Features ....................................................................................................... 4290
PCU iLB LPC Port 80h I/O Registers .................................................................. 4292
PCU – Power Management Controller (PMC) ........................................................ 4299
30.1
30.2
30.3
30.4
30.5
30.6
30.7
30.8
31
Signal Descriptions ....................................................................................... 4262
Features ....................................................................................................... 4262
Use.............................................................................................................. 4264
Register Map................................................................................................. 4264
SIO PWM 0 PCI Configuration Registers ............................................................ 4266
SIO PWM 0 Memory Mapped I/O Registers ........................................................ 4275
SIO PWM 1 PCI Configuration Registers ............................................................ 4278
SIO PWM 1 Memory Mapped I/O Registers ........................................................ 4287
Platform Controller Unit (PCU) Overview ............................................................. 4290
29.1
29.2
30
Signal Descriptions ........................................................................................ 4172
Features ....................................................................................................... 4173
Use.............................................................................................................. 4175
Register Map................................................................................................. 4176
SIO HSUART 0 PCI Configuration Registers ....................................................... 4178
SIO HSUART 0 Memory Mapped I/O Registers ................................................... 4187
SIO HSUART 1 PCI Configuration Registers ....................................................... 4220
SIO HSUART 0 Memory Mapped I/O Registers ................................................... 4229
Signal Descriptions ........................................................................................ 4429
Intel® Atom™ Processor E3800 Product Family
Datasheet
33.2
33.3
33.4
33.5
33.6
33.7
33.8
34
PCU – Intel® Legacy Block (iLB) Overview............................................................4478
34.1
34.2
34.3
35
Signal Descriptions .........................................................................................4551
Features .......................................................................................................4552
Use ..............................................................................................................4552
Register Map .................................................................................................4555
IO Mapped Registers.......................................................................................4555
PCU iLB 8254 Timers IO Registers ....................................................................4556
PCU – iLB – High Precision Event Timer (HPET) ....................................................4561
38.1
38.2
38.3
38.4
38.5
39
Signal Descriptions .........................................................................................4543
Features .......................................................................................................4544
Interrupts .....................................................................................................4545
References ....................................................................................................4547
Register Map .................................................................................................4547
IO Mapped Registers.......................................................................................4547
Indexed Registers ..........................................................................................4547
PCU iLB Real Time Clock (RTC) I/O Registers .....................................................4549
PCU – iLB – 8254 Timers.......................................................................................4551
37.1
37.2
37.3
37.4
37.5
37.6
38
Signal Descriptions .........................................................................................4515
Features .......................................................................................................4516
Use ..............................................................................................................4521
References ....................................................................................................4523
Register Map .................................................................................................4523
PCU iLB Low Pin Count (LPC) Bridge PCI Configuration Registers...........................4525
PCU iLB LPC BIOS Control Memory Mapped I/O Registers ....................................4542
PCU – iLB – Real Time Clock (RTC) .......................................................................4543
36.1
36.2
36.3
36.4
36.5
36.6
36.7
36.8
37
Signal Descriptions .........................................................................................4478
Features .......................................................................................................4479
PCU iLB Interrupt Decode and Route .................................................................4481
PCU – iLB – Low Pin Count (LPC) Bridge ...............................................................4515
35.1
35.2
35.3
35.4
35.5
35.6
35.7
36
Features .......................................................................................................4430
Use ..............................................................................................................4438
References ....................................................................................................4438
Register Map .................................................................................................4438
PCU SMBUS PCI Configuration Registers ............................................................4440
PCU SMBUS Memory Mapped I/O Registers........................................................4454
PCU SMBUS I/O Registers................................................................................4466
Features .......................................................................................................4561
References ....................................................................................................4563
Register Map .................................................................................................4563
Memory Mapped Registers...............................................................................4563
PCU iLB High Performance Event Timer (HPET) Memory Mapped IO Registers .........4564
PCU – iLB – GPIO..................................................................................................4572
39.1
39.2
39.3
39.4
39.5
39.6
Signal Descriptions .........................................................................................4572
Features .......................................................................................................4572
Legacy Use....................................................................................................4573
Memory Mapped Use ......................................................................................4573
Register Map .................................................................................................4574
GPIO Registers ..............................................................................................4575
Intel® Atom™ Processor E3800 Product Family
Datasheet
9
39.7
39.8
39.9
39.10
40
GPIO
GPIO
GPIO
GPIO
S0
S0
S5
S5
IO Addressed Registers .......................................................... 4577
Memory Addressed Registers .................................................. 4601
IO Addressed Registers .......................................................... 5045
Memory Address Map............................................................. 5059
Features ....................................................................................................... 5282
PCU – iLB – IO APIC ............................................................................................. 5284
41.1
41.2
41.3
41.4
42
iLB
iLB
iLB
iLB
PCU – iLB – Interrupt Decoding and Routing ........................................................ 5282
40.1
41
PCU
PCU
PCU
PCU
Features ....................................................................................................... 5284
Use.............................................................................................................. 5286
Indirect I/O APIC Registers ............................................................................. 5287
PCU iLB IO APIC Memory Mapped I/O Registers ................................................. 5288
PCU – iLB – 8259 Programmable Interrupt Controllers (PIC) ............................... 5290
42.1
42.2
Features ....................................................................................................... 5290
IO Mapped Registers ...................................................................................... 5297
42.3 PCU iLB 8259 Interrupt Controller (PIC) I/O Registers .................................................. 5299
Figures
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SoC Block Diagram .................................................................................28
Signals (1 of 2) ......................................................................................36
Signals (2 of 2) ......................................................................................37
Physical Address Space - DRAM & MMIO ....................................................70
Physical Address Space - Low MMIO ..........................................................71
Physical Address Space - DOS DRAM .........................................................72
Physical Address Space - SMM and Non-Snoop Mappings .............................73
Bus 0 PCI Devices and Functions ..............................................................78
Clocking Example ...................................................................................80
Idle Power Management Breakdown of the Processor Cores ..........................90
Package C-state Entry and Exit .................................................................92
RTC Power Well Timing Diagrams..............................................................98
G3/S5 to S0 Cold Boot Sequence ............................................................ 100
S0 to S3 to S4/S5 (Power Down) Sequence without S0ix ........................... 103
Definition of Differential Voltage and Differential Voltage Peak-to-Peak ........ 129
Definition of Pre-emphasis ..................................................................... 129
eMMC DC Bus signal level ...................................................................... 132
Definition of VHYS in Table 169 .............................................................. 144
Crystal Clock Timing ............................................................................. 148
SVID Timing Diagram............................................................................ 150
DDR3L DQ Setup/Hold Relationship to/from DQSP/DQSN (Read Operation) .. 152
DDR3L DQ and DM Valid before and after DQSP/DQSN (Write Operation) ..... 153
DDR3L Write Pre-amble Duration ............................................................ 153
DDR3L Write Post-amble Duration........................................................... 153
DDR3L Command Signals Valid before and after CK Rising Edge.................. 153
DDR3L CKE Valid before and after CK Rising Edge ..................................... 154
DDR3L CS# Valid before and after CK Rising Edge .................................... 154
DDR3L ODT Valid before CK Rising Edge .................................................. 154
Intel® Atom™ Processor E3800 Product Family
Datasheet
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80
DDR3L Clock Cycle Time ....................................................................... 154
DDR3L Skew between System Memory Differential Clock Pairs (CKP/CKN) ... 155
DDR3L CK High Time ............................................................................ 155
DDR3L CK Low Time ............................................................................. 155
DDR3L DQS Falling Edge Output Access Time to CK Rising Edge ................. 155
DDR3L DQS Falling Edge Output Access Time From CK Rising Edge ............. 156
DDR3L CK Rising Edge Output Access Time to the 1st DQS Rising Edge ....... 156
VGA_DDCDATA, and VGA_DDCCLK Timing Diagram .................................. 160
Input Glitch Rejection of Low-Power Receivers ......................................... 161
MIPI-CSI-2 Clock Definition ................................................................... 162
MIPI-CSI-2 Data to Clock Timing Definitions ............................................ 163
SD Card Timing Diagram (DDR50) .......................................................... 164
SD card Output Timing Diagram (SDR25) ................................................ 165
SD Card Input Timing Diagram (SDR12).................................................. 165
SD Card Input Timing Diagram (Default) ................................................. 166
SD card Output Timing Diagram (Default)................................................ 167
SD Card Input Timing Diagram (High Speed) ........................................... 168
SD card Output Timing Diagram (High Speed).......................................... 168
SDIO Timing Diagram (DDR50) .............................................................. 169
SDIO Output Timing Diagram (SDR25).................................................... 170
SDIO Output Timing Diagram (SDR12).................................................... 170
SDIO Input Timing Diagram (SDR12/25) ................................................. 171
eMMC* Output Timing Diagram (High Speed Mode) .................................. 172
eMMC* DDR Timings............................................................................. 172
eMMC Clock Signal Timing Diagram (HS200 Mode) ................................... 173
eMMC* Input Timing Diagram (High Speed Mode) .................................... 173
eMMC Input Timing Diagram (HS200 Mode) ............................................. 174
USB Rise and Fall Times ........................................................................ 178
USB Full Speed Load............................................................................. 179
USB Differential Data Jitter for Low/Full- Speed ........................................ 179
USB Differential-to-EOP Transition Skew and EOP Width for Low/Full-Speed . 179
USB 3.0 Signals AC Specification ............................................................ 180
ULPI Timing Diagram ............................................................................ 181
V/I Curves for HDA_SDO buffers ............................................................ 182
Maximum AC Waveforms for 1.5 V Signaling ............................................ 185
I2S Slave Port Timings in I2S Mode ......................................................... 187
I2S Slave Port Timings in PCM Short Frame Mode ..................................... 187
I2S Slave Port Timings in PCM Long Frame Mode ...................................... 188
PCI Express* Transmitter Eye ................................................................ 190
PCI Express* Receiver Eye .................................................................... 190
SPI NOR timing .................................................................................... 193
SMBus Transaction ............................................................................... 194
SMBus Timeout .................................................................................... 194
Valid Delay from Rising Clock Edge ......................................................... 195
Output Enable Delay ............................................................................. 195
Float Delay .......................................................................................... 196
Setup and Hold Times ........................................................................... 196
Definition of Timing for F/S-Mode Devices on I2C Bus................................ 198
Definition of Timing for High Speed-Mode Devices on I2C Bus..................... 200
UART Timing Diagram ........................................................................... 201
JTAG Timing Diagram ........................................................................... 202
TAP Valid Delay Timing Waveform .......................................................... 203
Intel® Atom™ Processor E3800 Product Family
Datasheet
11
Figure 81
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82
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101
102
103
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108
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111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
Test Reset (TAP_TRST#), Async GTL Input and PROCHOT# Timing Waveform ...
203
Clock Cycle Time .................................................................................. 204
Clock Timing ........................................................................................ 204
Valid Delay from Rising Clock Edge ......................................................... 204
Setup and Hold Times ........................................................................... 204
Float Delay .......................................................................................... 205
Pulse Width.......................................................................................... 205
Output Enable Delay ............................................................................. 205
Differential Clock Waveform (Measured Single-ended) ............................... 206
Differential Clock Waveform (Using Differential Probe for Measurement)....... 206
Package Mechanical Drawing .................................................................. 208
Soc Transaction Router Register Map....................................................... 317
HDMI Overview .................................................................................... 411
DisplayPort* Overview........................................................................... 412
3D Graphics Block Diagram .................................................................... 414
Camera Connectivity ........................................................................... 1039
Image Processing Components ............................................................. 1042
MIPI-CSI Bus Block Diagram ................................................................ 1046
MIPI CSI Register Map......................................................................... 1049
SD Memory Card Bus Topology ............................................................. 1747
SDIO Device Bus Topology ................................................................... 1748
eMMC Interface .................................................................................. 1748
Storage Control Cluster Register Map .................................................... 1750
SATA Register Map ............................................................................. 1923
xHCI and EHCI Port Mapping ................................................................ 2114
USB Host Controller Register Map ......................................................... 2118
Intel® HD Audio Register Map .............................................................. 2665
Audio Cluster Block Diagram ................................................................ 2801
Memory Connections for LPE ............................................................... 2802
SSP CCLK Structure ............................................................................ 2806
Programmable Serial Protocol Format .................................................... 2812
Programmable Serial Protocol Format (Consecutive Transfers) .................. 2812
Low Power Engine for Audio Register Map .............................................. 2818
PCIe* 2.0 Lane 0 Signal Example.......................................................... 3180
Root Port Configuration Options ............................................................ 3181
PCI Express Register Map .................................................................... 3184
SPI Interface Signals........................................................................... 3788
Clock Phase and Polarity ...................................................................... 3790
SIO - SPI Register Map........................................................................ 3792
Data Transfer on the I2C Bus................................................................ 3821
START and STOP Conditions ................................................................. 3822
Seven-Bit Address Format.................................................................... 3823
Ten-Bit Address Format ....................................................................... 3823
Master Transmitter Protocol ................................................................. 3824
Master Receiver Protocol...................................................................... 3825
START Byte Transfer ........................................................................... 3826
SIO - I2C Register Map ........................................................................ 3829
UART Data Transfer Flow ..................................................................... 4173
SIO - HSUART Register Map ................................................................. 4177
PWM Signals ...................................................................................... 4262
PWM Block Diagram ............................................................................ 4263
SIO - PWM Register Map...................................................................... 4265
Intel® Atom™ Processor E3800 Product Family
Datasheet
Figure
Figure
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Figure
133
134
135
136
137
138
139
140
Flash Descriptor Sections .....................................................................4369
Dual Output Fast Read Timing...............................................................4375
PCU - SMBus Register Map ...................................................................4439
LPC Interface Diagram .........................................................................4517
PCU - iLB - LPC Register Map ................................................................4524
SIO - I2C Register Map.........................................................................4575
Detailed Block Diagram ........................................................................5285
MSI Address and Data .........................................................................5286
Tables
Table
Table
Table
Table
Table
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Table
Table
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Intel® Atom™ Processor E3800 Product Family SKUs .................................. 35
Platform Power Well Definitions ................................................................ 38
Default Buffer State Definitions ................................................................ 39
DDR3L System Memory Signals................................................................ 40
PCI Express* 2.0 Interface Signals ........................................................... 41
USB 2.0 Interface Signals........................................................................ 41
USB 2.0 HSIC Interface Signals................................................................ 42
USB 3.0 Interface Signals........................................................................ 42
USB 2.0 Device Interface Signals.............................................................. 43
USB 3.0 Device Interface Signals.............................................................. 43
SATA 2.0 Interface Signals ...................................................................... 44
Integrated Clock Interface Signals ............................................................ 44
Digital Display Interface Signals ............................................................... 45
VGA Interface Signals ............................................................................. 46
MIPI CSI Interface Signals....................................................................... 46
HD Audio Interface Signals ...................................................................... 47
LPE Interface Signals .............................................................................. 48
Storage Control Cluster (eMMC, SDIO, SD) Interface Signals........................ 48
High Speed UART Interface Signals........................................................... 49
SIO - I2C Interface Signals ...................................................................... 50
SIO - Serial Peripheral Interface (SPI) Signals............................................ 50
PCU - iLB - Real Time Clock (RTC) Interface Signals .................................... 51
PCU - iLB - LPC Bridge Interface Signals .................................................... 52
PCU - Serial Peripheral Interface (SPI) Signals ........................................... 52
PCU - System Management Bus (SMBus) Interface Signals .......................... 53
PCU - Power Management Controller (PMC) Interface Signals ....................... 53
JTAG and Debug Interface Signals ............................................................ 54
Miscellaneous Signals and Clocks.............................................................. 54
GPIO Signals ......................................................................................... 55
Power and Ground Pins ........................................................................... 60
Straps .................................................................................................. 62
Fixed IO Register Access Method Example (P80 Register) ............................ 63
Fixed Memory Mapped Register Access Method Example (IDX Register) ......... 63
Referenced IO Register Access Method Example (HSTS Register) .................. 64
Memory Mapped Register Access Method Example (_MBAR Register)............. 64
PCI Register Access Method Example (VID Register) ................................... 64
PCI CONFIG_ADDRESS Register (IO PORT CF8h) Mapping ........................... 65
PCI Configuration Memory Bar Mapping..................................................... 66
MCR Description..................................................................................... 66
MCRX Description ................................................................................... 67
Intel® Atom™ Processor E3800 Product Family
Datasheet
13
14
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
Table
Table
Table
Table
78
79
80
81
Table
Table
Table
Table
82
83
84
85
Table
Table
Table
Table
Table
86
87
88
89
90
Register Access Types and Definitions .......................................................67
Fixed Memory Ranges in the Platform Controller Unit (PCU)..........................74
Fixed IO Ranges in the Platform Controller Unit (PCU)..................................75
Movable IO Ranges Decoded by PCI Devices on the IO Fabric .......................76
PCI Devices and Functions .......................................................................76
SoC Clock Inputs ....................................................................................81
SoC Clock Outputs ..................................................................................81
SoC Sx-States to SLP_S*# ......................................................................84
General Power States for System ..............................................................85
ACPI PM State Transition Rules .................................................................85
Processor Core/ States Support ................................................................86
SoC Graphics Adapter State Control ..........................................................86
Main Memory States................................................................................87
PCI Express* States ................................................................................87
G, S and C State Combinations.................................................................87
D, S and C State Combinations .................................................................88
Coordination of Core/Module Power States at the Package Level....................91
RTC Power Well Timing Parameters ...........................................................98
S4/S5 to S0 (Power Up) Sequence .......................................................... 101
S3/S4/S5 to S0 Cause of Wake Events .................................................... 104
Types of Resets .................................................................................... 106
Temperature Reading Based on DTS (If TJ-MAX =90oC) ............................ 108
Intel® Atom™ Processor E3800 Product Family Thermal Specifications......... 111
Storage Conditions Prior to Board Attach.................................................. 112
Power Rail DC Specs and Max Current ..................................................... 113
VCC and VNN Currents .......................................................................... 115
VCC and VNN DC Voltage Specifications ................................................... 115
IMVP7.0 Voltage Identification Reference ................................................. 116
ILB RTC Crystal Specification.................................................................. 123
Integrated Clock Crystal Specification ...................................................... 124
R,G,B/VGA DAC Display DC specification (Functional Operating Range) ........ 125
VGA_DDCCLK, VGA_DDCDATA Signal DC Specification .............................. 126
VGA_HSYNC and VGA_VSYNC DC Specification ......................................... 126
DDI Main Transmitter DC specification ..................................................... 126
DDI AUX Channel DC Specification .......................................................... 127
DDI DDC Signal DC Specification (DDI[1:0]_DDCDATA, DDI[1:0]_DDCCLK) . 128
DDI DDC Misc Signal DC Specification (DDI[1:0]_HPD, DDI[1:0]_BKLTCTL,
DDI[1:0]_VDDEN, DDI[1:0]_BKLTEN) ..................................................... 128
PCI Express* DC Receive Signal Characteristics ........................................ 130
PCI Express* DC Transmit Characteristics ................................................ 130
PCI Express* DC Clock Request Input Signal Characteristics ....................... 130
MIPI HS-RX/MIPI LP-RX Minimum, Nominal, and Maximum Voltage Parameters .
130
SDIO DC Specification ........................................................................... 131
SD Card DC Specification ....................................................................... 131
eMMC 4.5 Signal DC Electrical Specifications ............................................ 132
TAP Signal Group DC Specification (TAP_TCK, TAP_TRSRT#, TAP_TMS, TAP_TDI)
133
TAP Signal Group DC Specification (TAP_TDO) .......................................... 133
TAP Signal Group DC Specification (TAP_PRDY#, TAP_PREQ#).................... 134
DDR3L Signal Group DC Specifications..................................................... 134
HDA Signal Group DC Specifications ........................................................ 135
SATA TX/RX Signal Group DC Specifications ............................................. 139
Intel® Atom™ Processor E3800 Product Family
Datasheet
Table 91
Table 92
Table 93
Table 94
Table 95
Table 96
Table
Table
Table
Table
97
98
99
100
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
101
102
104
103
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
LPC Signal Group DC Specification (LPC_V1P8V3P3_S = 1.8V (ILB_LPC_AD][3:0],
ILB_LPC_FRAME#, ILB_LPC_SERIRQ, ILB_LPC_CLKRUN#)) ....................... 139
LPC Signal Group DC Specification LPC_V1P8V3P3_S = 3.3V (ILB_LPC_AD[3:0],
ILB_LPC_FRAME#, ILB_LPC_CLKRUN#)................................................... 140
SPI Signal Group DC Specification (PCU_SPI_MISO, PCU_SPI_CS[1:0]#,
PCU_SPI_MOSI, PCU_SPI_CLK).............................................................. 140
Power Management 1.8V Suspend Well Signal Group DC Specification ......... 141
PMC_RSTBTN# 1.8V Core Well Signal Group DC Specification..................... 142
Power Management & RTC Well Signal Group DC Specification (PMC_RSMRST#,
PMC_CORE_PWROK, ILB_RTC_RST#) ..................................................... 142
iLB RTC Well DC Specification (ILB_RTC_TEST#) ...................................... 142
ILB RTC Oscillator Optional DC Specification (ILB_RTC_X1) ........................ 142
PROCHOT# Signal Group DC Specification ............................................... 143
SVID Signal Group DC Specification (SVID_DATA, SVID_CLK, SVID_ALERT#) ....
143
GPIO 3.3V Core Well Signal Group DC Specification(GPIO_S0_SC[101:0]) ... 144
GPIO 3.3V Suspend Well Signal Group DC Specification (GPIO_S5[43:0]) .... 144
GPIO 1.8V Suspend Well Signal Group DC Specification (GPIO_S5[43:0]) .... 145
GPIO 1.8V Core Well Signal Group DC Specification (GPIO_S0_SC[101:0]) .. 145
I2C Signal Electrical Specifications .......................................................... 146
Crystal Clock Timings............................................................................ 147
Generic Clock Jitter AC Specification ....................................................... 148
25 MHz Platform Clock AC Specification ................................................... 149
SVID AC Specification ........................................................................... 149
DDR3L Interface Timing Specification...................................................... 150
DDI Main Transmitter AC specification..................................................... 156
DDI AUX Channel AC Specification .......................................................... 158
R,G,B / VGA DAC Display AC Specification ............................................... 158
VGA_HSYNC and VGA_VSYNC AC Specification ......................................... 159
VGA_DDCDATA, and VGA_DDCCLK Timing Specification ............................ 160
MIPI-CSI-2 Receiver Characteristics........................................................ 160
MIPI-CSI-2 Clock Signal Specification...................................................... 161
MIPI CSI 2 Data Clock Timing Specifications ............................................ 162
SD Card AC Specification....................................................................... 163
SD Card Default Speed AC Specification .................................................. 165
SD Card High Speed AC Specification ...................................................... 167
SDIO AC Specification ........................................................................... 168
eMMC 4.5 AC Characteristics.................................................................. 171
eMMC 4.5 AC Characteristics.................................................................. 173
SATA Specification and Interface Timings ................................................ 174
USB 2.0 AC specification (HIGH SPEED) .................................................. 176
USB 2.0 AC specification (FULL SPEED) ................................................... 177
USB 2.0 AC specification (LOW SPEED) ................................................... 177
ULPI Signals AC Specification ................................................................. 180
HDA_SDO 1.5V Buffer AC Specification ................................................... 182
HDA_SDI[x] 1.5V Buffer AC Specification ................................................ 183
1.5V Parameters for Maximum AC Signalling Waveforms ........................... 185
Resistance value for the AC rating Waveform ........................................... 185
I2S AC Timings .................................................................................... 186
I2S Master Mode AC Timing ................................................................... 188
PCI Express* Interface Timings .............................................................. 189
SUS Clock Timings ............................................................................... 191
PCU - SPI AC Specifications ................................................................... 191
Intel® Atom™ Processor E3800 Product Family
Datasheet
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Table
Table
Table
Table
139
140
141
142
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
179
180
181
182
183
184
185
186
187
188
189
PCU - SPI NOR AC Specifications............................................................. 192
SMBUS Clock Signal Timings .................................................................. 193
SMBus Timing ...................................................................................... 194
LPC AC Specifications (with loop back from ILB_LPC_CLK[0] to ILB_LPC_CLK[1])
195
I2C Fast/Standard Mode AC Specifications ................................................ 196
AC Specification for High Speed Mode I2C—Bus Devices ............................. 199
UART AC Specification ........................................................................... 201
JTAG AC Specification............................................................................ 201
Boundary Scan AC Specification.............................................................. 202
Ball Listing by Location with GPIO Muxed Functions ................................... 210
Memory Channel 0 DDR3L Signals........................................................... 275
Memory Channel 1 DDR3L Signals........................................................... 276
ECC Signals and Memory Channel 1 Signal Muxing .................................... 278
ECC Signals ......................................................................................... 278
Supported DDR3L Memory Size Per Rank ................................................. 279
Supported DDR3L ECC Memory Size Per Rank .......................................... 279
Supported DDR3L SO-DIMM Size ............................................................ 280
Summary of Memory Controller Message Bus Registers—Port 0x01 ............. 281
Summary of A-Unit Message Bus Registers—Port 0x00 .............................. 318
Summary of PCI Configuration Space Access I/O Registers......................... 321
Summary of B-Unit Message Bus Registers—Port 0x03 .............................. 323
Summary of C-Unit PCI Configuration Registers—0/0/0.............................. 338
Summary of C-Unit Message Bus Registers—Port 0x08 .............................. 345
Summary of Transaction Router P-Unit Message Bus Registers—Port 0x04 ... 351
Analog Display Interface Signals ............................................................. 407
Analog Port Characteristics..................................................................... 408
Display Physical Interfaces Signal Names ................................................. 409
Graphics clock frequency by SKUs........................................................... 414
Bay Trail-M/D Stepping POR for Video Encode/Decode ............................... 416
Hardware Accelerated Video Decode Codec Support .................................. 417
Summary of Graphics, Video and Display PCI Configuration Registers—0/2/0 419
Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB ......... 445
Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB ......... 635
Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB ....... 1027
Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB ....... 1033
CSI Signals ........................................................................................ 1038
GPIO Signals...................................................................................... 1038
Imaging Capabilities............................................................................ 1040
Summary of Image Signal Processor PCI Configuration Registers—0/2/0 .... 1050
Summary of Image Signal Processor Memory Mapped I/O Registers—ISPMMADR
1076
eMMC Signals..................................................................................... 1745
SDIO Signals...................................................................................... 1745
SD Card Signals ................................................................................. 1746
Summary of SDIO for Wifi PCI Configuration Registers—0/17/0 ................ 1751
Summary of SDIO for Wifi Memory Mapped I/O Registers—BAR ................ 1763
Summary of SD Card PCI Configuration Registers—0/18/0 ....................... 1807
Summary of SD Card Memory Mapped I/O Registers—BAR ....................... 1819
Summary of eMMC 4.5 PCI Configuration Registers—0/23/0 ..................... 1863
Summary of eMMC 4.5 Memory Mapped I/O Registers—BAR..................... 1875
Signals .............................................................................................. 1920
SATA Feature List ............................................................................... 1920
Intel® Atom™ Processor E3800 Product Family
Datasheet
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
190
191
192
193
194
195
196
197
198
199
200
201
202
203
Table 204
Table 205
Table 206
Table
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Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
Table 236
Table 237
SATA/AHCI Feature Matrix....................................................................1921
Summary of SATA PCI Configuration Registers—0/19/0 ............................1924
Summary of SATA Legacy I/O Registers—LBAR .......................................1953
Summary of SATA Index Pair I/O Registers—ABAR ..................................1959
Summary of SATA AHCI Memory Mapped I/O Registers—ABAR..................1961
Summary of SATA Primary Read Command I/O Registers—PCMDIDEBA......1998
Summary of SATA Primary Write Command I/O Registers—PCMDIDEBA .....2003
Summary of SATA Primary Read Control I/O Registers—PCTLIDEBA ...........2005
Summary of SATA Primary Write Control I/O Registers—PCTLIDEBA ..........2006
Summary of SATA Secondary Read Command I/O Registers—SCMDIDEBA..2007
Summary of SATA Secondary Write Command I/O Registers—SCMDIDEBA .2012
Summary of SATA Secondary Read Control I/O Registers—SCTLIDEBA .......2014
Summary of SATA Secondary Write Control I/O Registers—SCTLIDEBA ......2015
Summary of SATA Lane 0 Electrical Message Bus Registers—0xA3 (Global Offset
2200h) ..............................................................................................2017
Summary of SATA Lane 0 Electrical Message Bus Registers—0xA3 (Global Offset
2280h) ..............................................................................................2047
Summary of SATA Lane 1 Electrical Message Bus Registers—0xA3 (Global Offset
2400h) ..............................................................................................2065
Summary of SATA Lane 1 Electrical Message Bus Registers—0xA3 (Global Offset
2480h) ..............................................................................................2095
USB 3 SS Signals ................................................................................2113
USB 2 FS/HS Signals ...........................................................................2113
USB 2 HSIC Signals .............................................................................2113
Summary of USB xHCI PCI Configuration Registers—0/20/0......................2120
Summary of USB xHCI Memory Mapped I/O Registers—MBAR ...................2163
Summary of USB EHCI PCI Configuration Registers—0/29/0......................2345
Summary of USB EHCI Memory Mapped I/O Registers—MBAR ...................2369
Summary of USB EHCI Message Bus Registers—0x43...............................2427
USB 3.0 Device Signals ........................................................................2444
USB ULPI Device Signals ......................................................................2444
Summary of USB 3.0 Device PCI Configuration Registers—0/22/0..............2447
Summary of USB 3.0 Device PCI Configuration Registers—0/22/0..............2456
Summary of USB 3.0 Device Memory Mapped I/O Registers—BAR .............2461
Summary of USB 3.0 Device Memory Mapped I/O Registers—BAR .............2642
Signals ..............................................................................................2663
Summary of HD Audio PCI Configuration Registers—0/27/0 ......................2667
Summary of HD Audio Memory Mapped I/O Registers—AZLBAR.................2698
LPE Signals.........................................................................................2799
Clock Frequencies ...............................................................................2805
M/N Values, Examples .........................................................................2807
M/N Configurable Fields .......................................................................2808
Programmable Protocol Parameters .......................................................2813
Summary of Low Power Audio PCI Configuration Registers—0/21/0............2819
Summary of Memory Mapped I/O Registers—0/21/0 ................................2827
Summary of LPE Shim Memory Mapped I/O Registers—BAR ......................2837
Summary of Low Power Audio I2S0 Memory Mapped I/O Registers—BAR ....2864
Summary of Low Power Audio I2S0 Memory Mapped I/O Registers—BAR ....2884
Summary of Low Power Audio I2S0 Memory Mapped I/O Registers—BAR ....2904
Summary of Low Power Audio DMA0 Memory Mapped I/O Registers—
lpe_bridge.BAR ...................................................................................2924
Summary of Low Power Audio DMA1 Memory Mapped I/O Registers—
lpe_bridge.BAR ...................................................................................3037
Summary of TXE PCI Configuration Registers—0/26/0 ..............................3153
Intel® Atom™ Processor E3800 Product Family
Datasheet
17
Table
Table
Table
Table
Table
238
239
240
241
242
Table 243
Table 244
Table 245
Table 246
Table 247
Table 248
Table 249
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
18
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
Signals .............................................................................................. 3180
Possible Interrupts Generated From Events/Packets ................................ 3182
Interrupt Generated for INT[A-D] Interrupts........................................... 3182
Summary of PCI Express* PCI Configuration Registers—0/28/0 ................ 3186
Summary of PCI Express* Lane 0 Electrical Message Bus Registers—0xA6 (Global
Offset 200h) ...................................................................................... 3229
Summary of PCI Express* Lane 0 Electrical Message Bus Registers—0xA6 (Global
Offset 280h) ...................................................................................... 3259
Summary of PCI Express* Lane 1 Electrical Message Bus Registers—0xA6 (Global
Offset 400h) ...................................................................................... 3277
Summary of PCI Express* Lane 1 Electrical Message Bus Registers—0xA6 (Global
Offset 480h) ...................................................................................... 3307
Summary of PCI Express* Lane 2 Electrical Message Bus Registers—0xA6 (Global
Offset 600h) ...................................................................................... 3325
Summary of PCI Express* Lane 2 Electrical Message Bus Registers—0xA6 (Global
Offset 680h) ...................................................................................... 3355
Summary of PCI Express* Lane 3 Electrical Message Bus Registers—0xA6 (Global
Offset 800h) ...................................................................................... 3373
Summary of PCI Express* Lane 3 Electrical Message Bus Registers—0xA6 (Global
Offset 880h) ...................................................................................... 3403
Summary of DMA 1 PCI Configuration Registers—0/30/0.......................... 3421
Summary of SIO DMA 1 Memory Mapped I/O Registers—BAR ................... 3430
Summary of SIO DMA 2 PCI Configuration Registers—0/24/0 ................... 3604
Summary of SIO DMA 2 Memory Mapped I/O Registers—BAR ................... 3613
SPI Modes ......................................................................................... 3790
Summary of SPI PCI Configuration Registers—0/30/5 .............................. 3793
Summary of SPI Memory Mapped I/O Registers—BAR.............................. 3802
I2C[6:0] Signals ................................................................................. 3819
I2C Definition of Bits in First Byte.......................................................... 3823
Summary of I2C 0 PCI Configuration Registers—0/24/1 ........................... 3830
Summary of I2C 0 Memory Mapped I/O Registers—BAR ........................... 3839
Summary of I2C 1 PCI Configuration Registers—0/24/2 ........................... 3878
Summary of I2C 1 Memory Mapped I/O Registers—BAR ........................... 3888
Summary of I2C 2 PCI Configuration Registers—0/24/3 ........................... 3927
Summary of I2C 2 Memory Mapped I/O Registers—BAR ........................... 3937
Summary of I2C 3 PCI Configuration Registers—0/24/4 ........................... 3976
Summary of I2C 3 Memory Mapped I/O Registers—BAR ........................... 3986
Summary of I2C 4 PCI Configuration Registers—0/24/5 ........................... 4025
Summary of I2C 4 Memory Mapped I/O Registers—BAR ........................... 4035
Summary of I2C 5 PCI Configuration Registers—0/24/6 ........................... 4074
Summary of I2C 5 Memory Mapped I/O Registers—BAR ........................... 4084
Summary of I2C 6 PCI Configuration Registers—0/24/7 ........................... 4123
Summary of I2C 6 Memory Mapped I/O Registers—BAR ........................... 4133
UART 1 Interface Signals ..................................................................... 4172
UART 2 Interface Signals ..................................................................... 4173
Sclock Frequencies from M/N Settings ................................................... 4174
Baud Rates Achievable with Different DLAB Settings ................................ 4174
Summary of HSUART 0 PCI Configuration Registers—0/30/3 .................... 4178
Summary of HSUART 1 Memory Mapped I/O Registers—BAR .................... 4187
Summary of HSUART 1 PCI Configuration Registers—0/30/4 .................... 4220
Summary of HSUART 1 Memory Mapped I/O Registers—BAR .................... 4229
Example PWM Output Frequency and Resolution ..................................... 4264
Summary of PWM 0 PCI Configuration Registers—0/30/1 ......................... 4266
Summary of PWM 0 Memory Mapped I/O Registers—BAR ......................... 4275
Intel® Atom™ Processor E3800 Product Family
Datasheet
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
284
285
286
287
288
289
290
291
292
293
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
294
295
296
297
298
299
300
301
302
303
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
304
305
306
307
308
309
310
311
312
313
314
315
Table
Table
Table
Table
316
317
318
319
Table
Table
Table
Table
320
321
322
323
Table 324
Table
Table
Table
Table
Table
Table
Table
325
326
327
328
329
330
331
Summary of PWM 1 PCI Configuration Registers—0/30/2..........................4278
Summary of PWM 1 Memory Mapped I/O Registers—BAR .........................4287
Summary of PCU iLB LPC Port 80h I/O Registers—...................................4292
PMC Signals........................................................................................4299
Transitions Due to Power Failure ...........................................................4302
Transitions Due to Power Button............................................................4303
System Power Planes ...........................................................................4304
Causes of SMI and SCI.........................................................................4307
INIT# Assertion Causes .......................................................................4310
Summary of PCU iLB PMC Memory Mapped I/O Registers—PMC_BASE_ADDRESS
4311
Summary of PCI iLB PMC I/O Registers ..................................................4345
Summary of PCU iLB PMC I/O Registers—ACPI_BASE_ADDRESS................4348
SPI Signals.........................................................................................4366
SPI Flash Regions................................................................................4367
Region Size Versus Erase Granularity of Flash Components .......................4368
Region Access Control..........................................................................4370
Hardware Sequencing Commands and Opcode Requirements ....................4374
Recommended Pinout for 8-Pin Serial Flash Device ..................................4377
Recommended Pinout for 16-Pin Serial Flash Device.................................4377
Summary of PCU SPI for Firmware Memory Mapped I/O Registers—
SPI_BASE_ADDRESS ...........................................................................4381
UART Signals ......................................................................................4415
Baud Rate Examples ............................................................................4416
Register Access List .............................................................................4419
Summary of PCU iLB UART I/O Registers— .............................................4420
SMBus Signal Names ...........................................................................4430
I2C Block Read....................................................................................4434
Enable for PCU_SMB_ALERT# ...............................................................4436
Enables for SMBus Host Events .............................................................4436
Enables for the Host Notify Command ....................................................4436
Host Notify Format ..............................................................................4437
Summary of PCU SMBUS PCI Configuration Registers—0/31/3...................4440
Summary of PCU SMBUS Memory Mapped I/O Registers—SMB_Config_MBARL ...
4454
Summary of PCU SMBUS I/O Registers—SMB_Config_IOBAR ....................4466
iLB Signals .........................................................................................4479
NMI Sources .......................................................................................4480
Summary of PCU iLB Interrupt Decode and Route Memory Mapped I/O Registers—
ILB_BASE_ADDRESS ...........................................................................4481
LPC Signals ........................................................................................4516
SERIRQ, Stop Frame Width to Operation Mode Mapping ...........................4520
SERIRQ Interrupt Mapping....................................................................4521
Summary of PCU iLB Low Pin Count (LPC) Bridge PCI Configuration Registers—0/
31/0 ..................................................................................................4525
Summary of PCU iLB LPC BIOS Control Memory Mapped I/O Registers—
RCRB_BASE_ADDRESS ........................................................................4542
RTC Signals ........................................................................................4544
Register Bits Reset by ILB_RTC_RST# Assertion ......................................4546
I/O Registers Alias Locations.................................................................4547
RTC Indexed Registers .........................................................................4548
Summary of PCU iLB Real Time Clock (RTC) I/O Registers—......................4549
8254 Signals ......................................................................................4551
Counter Operating Modes .....................................................................4553
Intel® Atom™ Processor E3800 Product Family
Datasheet
19
20
Table
Table
Table
Table
332
333
334
335
Table
Table
Table
Table
Table
336
337
338
339
340
Table
Table
Table
Table
Table
Table
341
342
343
344
345
346
Register Aliases .................................................................................. 4555
Summary of PCU iLB 8254 Timers I/O Registers—................................... 4556
8254 Interrupt Mapping....................................................................... 4563
Summary of PCU iLB High Performance Event Timer (HPET) Memory Mapped I/O
Registers— ........................................................................................ 4564
GPIO Signals...................................................................................... 4572
Summary of PCU iLB GPIO S0 IO Registers—GPIO_BASE_ADDRESS .......... 4577
Summary of iLB GPIO S0 Memory Mapped I/O Registers—IOBASE ............ 4601
Summary of PCU iLB GPIO S5 IO Registers—GBASE + 80h....................... 5045
Summary of iLB GPIO S5 Memory Mapped I/O Registers—IOBASE + 0x2000 .....
5059
Summary of PCU iLB I/O APIC Memory Mapped I/O Registers— ................ 5288
Interrupt Controller Connections ........................................................... 5291
Interrupt Status Registers.................................................................... 5292
Content of Interrupt Vector Byte ........................................................... 5292
I/O Registers Alias Locations ................................................................ 5298
Summary of PCU iLB 8259 Interrupt Controller (PIC) I/O Registers— ......... 5299
Intel® Atom™ Processor E3800 Product Family
Datasheet
Revision History
Revision
Number
Description
Revision Date
1.0
Initial release.
1.5
Chapter 2, “Physical Interfaces”
• Updated the table details of the GPIO Signals for GPIO_S0_SC[046], GPIO_S0_SC[047],
GPIO_S0_SC[048], GPIO_S5[15], GPIO_S5[16], GPIO_S5[17].
December 2013
October 2013
Chapter 5, “Integrated Clock”
• Added table note (SoC Clock Outputs) that Intel recommends 25 MHz. 19.2 MHz is not
validated.
Chapter 6, “Power Management”
• De-featured C6IS for all SKUs.
• Updated the table details of the SoC Sx-States to SLPT_S*# for PMC_PLTRST# from 0 or
1 to High or Low to match platform understanding.
• Remove VCC and VNN from Bay Trail-M/D SoC Power Rail DC Specs & Max Current table.
Chapter 7, “Power Up and Reset Sequence”
• Updated the figure and notes of the S0 to S3 to S4/S5 (Power Down) Sequence.
• Updated the table of the S4/S5 to S0 (Power Up) Sequence for t3 parameter from 100
max to 95 min (no max).
Chapter 9, “Electrical Specifications”
• Updated the table details of the 25 MHz Platform Clock AC Specification.
Chapter 11, “Processor Core”
• Updated 11.1 note on Thermal management support.
Chapter 12, “System Memory Controller”
• Updated 12.2.2 table title and details for “Supported DDR3L Memory Size Per Rank” and
“Supported DDR3L SO-DIMM Size”.
Chapter 16, “Storage Control Cluster (eMMC, SDIO, SD Card)”
• Updated the supported SDIO/SD card bandwidth is up to 400Mbits per seconds.
Chapter 18, “USB Host Controller Interfaces (xHCI, EHCI)”
• Added figure note of the xHCI and EHCI Port Mapping.
• Updated USB configuration register to correctly reflect the power well.
Chapter 22, “Intel® Trusted Execution Engine (TXE)”
• Updated chapter title to Intel® Platform Trust Technology (PTT).
Chapter 29, “Platform Controller Unit (PCU) Overview”
• Added a note to Platform Clock Support section that Intel recommends 25 MHz as 19.2
MHz is not validated.
2.0
Chapter 7, “Power Up and Reset Sequence”
• Updated the 7.2.2 note 4
• OK to swap V1P0A and V1P8A
• Measurement point for timing is 90% (10% on power down)
February 2014
Chapter 9, “Electrical Specifications”
• Added S3 power spec per measurements
• Added generic clock jitter specs
Intel® Atom™ Processor E3800 Product Family
Datasheet
21
Revision
Number
2.5
Description
Revision Date
Chapter 2, “Physical Interfaces”
• Updated 2.28 RTC_VCC detail
April 2014
Chapter 7, “Power Up and Reset Sequence”
• Updated the 7.2.2 note 7
• Updated the 7.3.1 note 6 and note 7
• Measurement point for timing is 90% (10% on power down)
Chapter 9, “Electrical Specifications”
• Added 9.5.18 GPIO VIH max and VIL min
• Added 9.5.19 I2C VIH max and VIL min
3.0
July 2014
Chapter 2, “Physical Interfaces”
• Updated RTC_VCC detail
Chapter 7, “Power Up and Reset Sequence”
• Updated slew rate to 10ms.
• Measurement point for timing is 10% on power down
Chapter 9, “Electrical Specifications”
• Added 9.5.18 GPIO VIH max and VIL min
• Added 9.5.19 I2C VIH max and VIL min
Chapter 11, “Processor Core”
• Removed support on C1E and C6C
Chapter 14, “Graphics, Video and Display”
• Updated 14.10.11 MSR (MSR_READ) offset to 180000h
Chapter 16, “Storage Control Cluster (eMMC, SDIO, SD Card)”
• Updated the Preset value feature to not PoR.
• Updated SDIO support SDR12/25.
Chapter 22, “Intel® Trusted Execution Engine (TXE)”
• Updated name of chapter to “Intel® Trusted Execution Engine (TXE)”.
• Clarified use of descriptor mode and other requirements for the boot SPI.
• Added registers for Intel® TXE.
22
Intel® Atom™ Processor E3800 Product Family
Datasheet
Revision
Number
3.5
Description
Chapter 2, “Physical Interfaces”
• Changed Figure 3 USB_ULPI_REFCLK to output
Revision Date
September 2014
Chapter 5, “Integrated Clock”
• Updated the MCSI clock to 80-500 MHz
Chapter 7, “Power Up and Reset Sequence”
• Updated Table 58, max tolerance time, to 2000us - to avoid in rush current
• removed PMC_SUSPWRDNACK from figure 13
• updated PMC_SUSPWRDNACK in figure 14
Chapter 9, “Electrical Specifications”
• Added SPI NOR AC Spec
• Updated GPIO Vih/Vil min and max
• changed the I2S max clock frequency to 12.288 MHz
Chapter 11, “Processor Core”
• Added Note: “L1 has parity protection and L2 has an ECC Protection.”
Chapter 12, “System Memory Controller”
• Removed DECCSTAT OFFSET 61h register
Chapter 13, “SoC Transaction Router”
• Updated register TRR - OFFSET B1h
Chapter 22, “Intel® Trusted Execution Engine (TXE)”
• updated the SSP to support 24 bits data sample sizes
Chapter 29, “Platform Controller Unit (PCU) Overview”
• De-Featured Top Swap Mechanism
Intel® Atom™ Processor E3800 Product Family
Datasheet
23
Revision
Number
3.6
Description
Revision Date
January 2015
Chapter 1, “Introduction”
• Changed Figure 1, “SoC Block Diagram” on page 148
• Changed Chapter 1, “Terminology”
• Changed Chapter 1, “Display Controller”
• Changed Chapter 1, “Graphics and Media Engine”
• Changed Chapter 1, “SKU List”
Chapter 2, “Physical Interfaces”
• Changed Figure 3, “Signals (2 of 2)” on page 37
• Changed Chapter 2, “Pin States Through Reset”
• Changed Table 9, “USB 2.0 Device Interface Signals” on page 163
• Changed Table 13, “Digital Display Interface Signals” on page 165
• Changed Chapter 2, “PCU – iLB – Low Pin Count (LPC) Bridge Interface Signals”
• Changed Table 24, “PCU - Serial Peripheral Interface (SPI) Signals” on page 172
• Changed Table 30, “Power and Ground Pins” on page 180
Chapter 5, “Integrated Clock”
• Updated Table 60, “SoC Clock Outputs” on page 277
Chapter 6, “Power Management”
• Updated Table 118, “General Power States for System” on page 404
• Changed Chapter 33, “Package C-States”
Chapter 7, “Power Up and Reset Sequence”
• Updated Chapter 35, “G3 to S0”
• Updated Table 129, “S4/S5 to S0 (Power Up) Sequence” on page 424
• Updated Chapter 35, “S0 to S3 and S4/S5/G3 Sequence”
• Updated Chapter 7, “S0 to S3 to S4/S5 (Power Down) Sequence without S0ix”
• Updated Table 60, “S3/S4/S5 to S0 Cause of Wake Events” on page 104
• Updated Chapter 7, “Reset Behavior”
Chapter 34, “Thermal Management”
• Updated Chapter 34, “Thermal Management”
Chapter 9, “Electrical Specifications”
• Updated Table 133, “Intel® Atom™ Processor E3800 Product Family Thermal
Specifications” on page 432
• Updated Table 135, “Power Rail DC Specs and Max Current” on page 434
• Updated Table 66, “VCC and VNN Currents” on page 115
• Updated Table 72, “VGA_DDCCLK, VGA_DDCDATA Signal DC Specification” on page 126
• Updated Table 146, “DDI DDC Signal DC Specification (DDI[1:0]_DDCDATA,
DDI[1:0]_DDCCLK)” on page 449
• Updated Table 150, “PCI Express* DC Clock Request Input Signal Characteristics” on
page 451
• Updated Table 83, “SD Card DC Specification” on page 131
• Updated Table 84, “eMMC 4.5 Signal DC Electrical Specifications” on page 132
• Updated Table 85, “TAP Signal Group DC Specification (TAP_TCK, TAP_TRSRT#,
TAP_TMS, TAP_TDI)” on page 133
• Updated Table 86, “TAP Signal Group DC Specification (TAP_TDO)” on page 133
• Updated Table 87, “TAP Signal Group DC Specification (TAP_PRDY#, TAP_PREQ#)” on
page 134
• Updated Table 166, “Power Management & RTC Well Signal Group DC Specification
(PMC_RSMRST#, PMC_CORE_PWROK, ILB_RTC_RST#)” on page 463
• Updated Table 167, “iLB RTC Well DC Specification (ILB_RTC_TEST#)” on page 463
• Added Table 172, “GPIO 3.3V Suspend Well Signal Group DC Specification
(GPIO_S5[43:0])” on page 465
• Added Table 172, “GPIO 3.3V Suspend Well Signal Group DC Specification
(GPIO_S5[43:0])” on page 465
• Updated Table 103, “GPIO 1.8V Core Well Signal Group DC Specification
(GPIO_S0_SC[101:0])” on page 145
• Updated Table 104, “GPIO 1.8V Suspend Well Signal Group DC Specification
(GPIO_S5[43:0])” on page 145
• Updated Table 175, “I2C Signal Electrical Specifications” on page 466
24
Intel® Atom™ Processor E3800 Product Family
Datasheet
Revision
Number
3.6
Description
•
•
Updated Table 208, “PCU - SPI AC Specifications” on page 511
Updated Table 139, “PCU - SPI NOR AC Specifications” on page 192
Revision Date
January 2015
Chapter 12, “System Memory Controller”
• Updated Chapter 4, “Features”
Chapter 14, “Graphics, Video and Display”
• Updated Chapter 5, “Features”
• Updated Chapter 5, “Video Engine”
• Updated Table 43, “Hardware Accelerated Video Decode Codec Support” on page 218
Chapter 6, “MIPI-Camera Serial Interface (CSI) and ISP”
• Updated Chapter 6, “Features”
• Updated Table 45, “Imaging Capabilities” on page 223
Chapter 8, “Storage Control Cluster (eMMC, SDIO, SD Card)”
• Updated Chapter 8, “SDIO/SD Card Interface Features”
Chapter 7, “Low Power Engine (LPE) for Audio (I2S)”
• Updated Chapter 7, “External Timer”
• Updated Table 47, “Clock Frequencies” on page 240
Chapter 19, “PCU – Power Management Controller (PMC)”
• Updated Table 71, “Transitions Due to Power Button” on page 312
• Updated Chapter 19, “PMC_RSTBTN# Signal”
• UpdatedTable 72, “System Power Planes” on page 313
• Updated Table 73, “Causes of SMI and SCI” on page 316
Chapter 20, “PCU – Serial Peripheral Interface (SPI)”
• Updated Chapter 20, “Descriptor Mode”
Chapter 21, “PCU – Universal Asynchronous Receiver/Transmitter (UART)”
• Updated Chapter 21, “UART Enable/Disable”
Chapter 31, “PCU – System Management Bus (SMBus)”
• Added Chapter 31, “SPD Write Disable”
Chapter 22, “PCU – Intel® Legacy Block (iLB) Overview”
• Updated Chapter 22, “Non-Maskable Interrupt”
§§
Intel® Atom™ Processor E3800 Product Family
Datasheet
25
26
Intel® Atom™ Processor E3800 Product Family
Datasheet
Introduction
1
Introduction
The Intel® Atom™ Processor E3800 Product Family is the Intel Architecture (IA) SoC
that integrates the next generation Intel® processor core, Graphics, Memory Controller,
and I/O interfaces into a single system-on-chip solution.
The figures below show the system level block diagram of the SoC. Refer to the
subsequent chapters for detailed information on the functionality of the different
interface blocks.
Notes:
Throughout this document Intel® Atom™ Processor E3800 Product Family is referred to
as the SoC or Processor.
This document details features of the silicon only. For platform support and software,
contact your Intel representative.
Intel® Atom™ Processor E3800 Product Family
Datasheet
27
Introduction
Figure 1.
SoC Block Diagram
JTAG
IO
OOE Intel®
AtomTM
Processor Core
OOE Intel®
AtomTM
Processor Core
OOE Intel®
AtomTM
Processor Core
1MiB L2
OOE Intel®
AtomTM
Processor Core
1MiB L2
Video
P-Unit
3D Graphics
IO
HD Audio
2
IO
2
PWM
HSUART
SPI
IO
IO
7
I2C
IO
4
PCIe*
IO
IO
2
3
SATA
SD/MMC
SIO
O
I2S/PCM
IO
Integrated Clock
O
Memory
Controller
Channel
1
APIC
8259
LPE
3
IO
I/O
Fabric
HPET
ILB
GPIO
Channel
0
Platform Control Unit
IO
IO
28
MIPI-CSI
Camera
ISP
3
SoC
Transaction
Router
8254
RTC
IO
GPIO
IO
LPC
PMC
IO
SPI
IO
UART
SMB
IO
O
IO
IO
3.0 (SS)
IO
USB
1/2/3
VGA
IO
IO
DDI
1/2.0 (HS/FS)
4
IO
2.0 (HSIC)
2
IO
USB
Dev
2
Display
IO
IO
SVID
3.0 (SS)
ULPI (HS/FS)
IO
IO
Intel® Atom™ Processor E3800 Product Family
Datasheet
Introduction
1.1
Terminology
Term
Description
ACPI
Advanced Configuration and Power Interface
Cold Reset
A Host reset with Power Cycle. See Table 132
CRT
Cathode Ray Tube
CRU
Clock Reset Unit
DP
Display Port
DTS
Digital Thermal Sensor
EMI
Electro Magnetic Interference
eDP
embedded Display Port
HDMI
High Definition Multimedia Interface. HDMI supports standard, enhanced, or highdefinition video, plus multi-channel digital audio on a single cable. HDMI transmits
all Advanced Television Systems Committee (ATSC) HDTV standards and supports
8-channel digital audio, with bandwidth to spare for future requirements and
enhancements (additional details available at http://www.hdmi.org/).
IGD
Internal Graphics Unit
®
Intel
TXE
Intel® Trusted Execution Engine
LCD
Liquid Crystal Display
LPE
Low Power Engine
MIPI CSI
MIPI Camera Interface Specification
MPEG
Moving Picture Experts Group
MSI
Message Signaled Interrupt. MSI is a transaction initiated outside the host,
conveying interrupt information to the receiving agent through the same path that
normally carries read and write commands.
MSR
Model Specific Register, as the name implies, is model-specific and may change
from processor model number (n) to processor model number (n+1). An MSR is
accessed by setting ECX to the register number and executing either the RDMSR
or WRMSR instruction. The RDMSR instruction will place the 64 bits of the MSR in
the EDX: EAX register pair. The WRMSR writes the contents of the EDX: EAX
register pair into the MSR.
PCIe*
PCI Express* (PCIe*) is a high-speed serial interface. The PCIe* configuration is
software-compatible with the existing PCI specifications.
PWM
Pulse Width Modulation
Rank
A unit of DRAM corresponding to the set of SDRAM devices that are accessed in
parallel for a given transaction. For a 64-bit wide data bus using 8-bit (x8) wide
SDRAM devices, a rank would be eight devices. Multiple ranks can be added to
increase capacity without widening the data bus, at the cost of additional electrical
loading.
SCI
System Control Interrupt. SCI is used in the ACPI protocol.
SDRAM
Synchronous Dynamic Random Access Memory
SERR
System Error. SERR is an indication that an unrecoverable error has occurred on
an I/O bus.
Intel® Atom™ Processor E3800 Product Family
Datasheet
29
Introduction
Term
1.2
Description
SMI
System Management Interrupt is used to indicate any of several system conditions
(such as thermal sensor events, throttling activated, access to System
Management RAM, chassis open, or other system state related activity).
SIO
Serial I/O
TMDS
Transition-Minimized Differential Signaling. TMDS is a serial signaling interface
used in DVI and HDMI to send visual data to a display. TMDS is based on lowvoltage differential signaling with 8/10b encoding for DC balancing.
VCO
Voltage Controlled Oscillator
Warm
Reset
Host Reset without Power Cycle. See Table 132
Feature Overview
All features subject to software availability.
1.2.1
Processor Core
See Chapter 3, “Processor Core” for more details.
• Up to four IA-compatible low power Intel® processor cores
— One thread per core
• Two-wide instruction decode, out of order execution
• On-die, 32 KB 8-way L1 instruction cache and 24 KB 6-way L1 data cache per core
• On-die, 1 MB, 16-way L2 cache, shared per two cores
• L1 has parity protection and L2 has ECC protection
• 36-bit physical address, 48-bit linear address size support
• Supported C-states: C0, C1, C6
• Supports Intel® Virtualization Technology (Intel® VT-x)
1.2.2
System Memory Controller
See Chapter 4, “System Memory Controller” for more details.
• Supports up to two channels of DDR3L
• 64 bit data bus for each channel
• ECC supported in single channel mode only
• Supports x8 and x16 DDR3L SDRAM device data widths
• Supports DDR3L with 1066 or 1333 MT/s data rates
— Total memory bandwidth supported is 8.5 GB/s (for 1066 MT/s single channel)
scalable to 21.3GB/s(for 1333 MT/s dual channel)
• Supports different physical mappings of bank addresses to optimize performance
30
Intel® Atom™ Processor E3800 Product Family
Datasheet
Introduction
• Out-of-order request processing to increase performance
• Aggressive power management to reduce power consumption
• Proactive page closing policies to close unused pages
1.2.3
Display Controller
See Chapter 5, “Graphics, Video and Display” for more details.
• Support 2 DDI ports to enable eDP 1.3, DP 1.1a, DVI, or HDMI 1.4a
• Support 2 panel power sequence for 2 eDP ports
• Support Audio on DP and HDMI
• Supports Intel® Display Power Saving Technology (DPST) 6.0, Panel Self Refresh
(PSR) and Display Refresh Rate Switching Technology (DRRS)
• Supports one VGA port
Note:
1.2.4
These feature are not applicable to the E3805 SKU.
Graphics and Media Engine
See Chapter 5, “Graphics, Video and Display” for more details.
• Intel's 7th generation (Gen 7) graphics and media encode/decode engine
• VED video decoder in addition to Gen 7 Media decoder
• Supports DX*11, OpenGL 3.0 (OGL 3.0), OpenCL 1.2 (OCL 1.2), OpenGLES 2.0
(OGLES 2.0)
• GPU shader is capable of up to 8 gigaflops
• 4x anti-aliasing
• Full HW acceleration for decode of Up to 1080p@60fps and 3x 4kx2k @30fps
(H.264/JPEG/MJPEG/MVC/MPEG-2 /WMV9/VC1)
• Full HW acceleration for encode of Up to 1080p@60fps and 1x 4kx2k @30fps
(H.264)
• Supports 2.0 Stereoscopic 3D Stretch
• Polyphase 8 tap scaling
• HD HQV
Note:
1.2.5
These feature are not applicable to the E3805 SKU.
Image Signal Processor
See Chapter 6, “MIPI-Camera Serial Interface (CSI) and ISP” for more details.
• Support up to three MIPI CSI ports
• Support for up to 24MP sensors
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31
Introduction
• Supports Stereoscopic Video
1.2.6
Power Management
See Chapter 33, “Power Management” for more details.
• ACPI 5.0 support
• Processor states: C0-C6
• Display device states: D0, D3
• Graphics device states: D0, D3
• System sleep states: S0, S3, S4, S5
• Dynamic I/O power reductions (disabling sense amps on input buffers, tristating
output buffers)
• Active power-down of display links
• Downloadable power management firmware
1.2.7
PCI Express*
The SoC has four PCI Express* lanes and up to four PCI Express root ports, each
supporting the PCI Express Base specification Rev 2.0 at a maximum of 5 Gbit/s data
transfer rates.The root ports configurations are flexible and can be configured to be (4)
x1, (2) x2’s, (1) x2 plus (2) x1’s, and (1) x4.
See Chapter 21, “MIPI-Camera Serial Interface (CSI) and ISP” for more details.
1.2.8
SATA
See Chapter 16, “Serial ATA (SATA)” for more details.
• Two (2) SATA Revision 2.0 ports (eSATA capable)
• Legacy IDE (including IRQ)/Native IDE/AHCI appearance to OS
• Partial/Slumber power management modes with wake
• Capable of 3 Gbit/s transfer rate
1.2.9
USB xHCI Controller
See Chapter 10, “USB Host Controller Interfaces (xHCI, EHCI)” for more details.
• Supports USB 3.0/2.0/1.1
• Implements xHCI software host controller interface
• One USB 3.0 Super Speed (SS) port
• Four ports multiplexed with EHCI controller that are High Speed/Full Speed (HS/FS)
• Two High Speed Inter Chip (HSIC) ports compliant with USB 2.0
32
Intel® Atom™ Processor E3800 Product Family
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Introduction
1.2.10
USB 2.0 EHCI Controller
See Chapter 10, “USB Host Controller Interfaces (xHCI, EHCI)” for more details.
• Internal Rate Matching Hub to support USB 1.1 to 2.0 devices
• Four Ports multiplexed with xHCI controller
• Enhanced EHCI descriptor caching
1.2.11
USB 2.0 (ULPI) and 3.0 Device
See Chapter 9, “USB Device Controller Interfaces (3.0, ULPI)” for more details.
• Supports one USB 3.0 SS port with USB device compatibility
• Supports one ULPI port with HS/LS support
1.2.12
Audio Controllers
1.2.12.1
Low Power Engine (LPE) Audio
LPE is a complete audio solution based on an internal audio processing engine, which
includes three I2S output ports. See Chapter 7, “Low Power Engine (LPE) for Audio
(I2S)” for more details.
LPE supports:
• I2S and DDI with dedicated DMA
• MP3, AAC, AC3/DD+, WMA9, PCM (WAV)
Note:
1.2.12.2
Codecs supported depend on software and may be different.
Intel® High Definition Audio (Intel® HD Audio)
See Chapter 18, “Intel® High Definition Audio” for more details.
• Four in + four out streams (Only 3 used)
• One stream for each DDI, available for HDMI and DP
• No wake on audio (modem) support
1.2.13
Storage Control Cluster (eMMC, SDIO, SD)
See Chapter 8, “Storage Control Cluster (eMMC, SDIO, SD Card)” for more details.
• Supports one SDIO 3.0 controller
• Supports one eMMC 4.5 controller
• Supports one SDXC controller
Intel® Atom™ Processor E3800 Product Family
Datasheet
33
Introduction
1.2.14
Intel® Trusted Execution Engine (Intel® TXE)
Intel® TXE is a security co-processor used to enable security features.
See Chapter 17, “Intel® Trusted Execution Engine (TXE)” for more details.
Security features include:
• Isolated execution environment for crypto operations (SKU-enabled)
• Supports secure boot - with customer programmable keys to secure code
Note:
1.2.15
The SoC requires TXE firmware in the PCU SPI flash image to function. Contact your
Intel® representative for details.
Serial I/O (SIO)
See Chapter 12, “Serial IO (SIO) Overview” for links to more information about each
interface.
• Controller for external devices via SPI, UART, I2C or PWM
• Each port is multiplexed with general purpose I/O for configurations flexibility
• Supports up to 7 I2C, 2 HSUART, 2 PWM, 1 SPI interface
1.2.16
Platform Control Unit (PCU)
The platform controller unit is a collection of HW blocks, including SMBus, UART,
debug/boot SPI and Intel legacy block (iLB), that are critical to implement a Windows*
compatible platform. See Chapter 18, “Platform Controller Unit (PCU) Overview” for
links to more information about each interface.
Key PCU features include:
• SMBus Host controller - supports SMBus 2.0 specification
• Universal Asynchronous Receiver/Transmitter (UART) with COM1 interface
• A Serial Peripheral Interface (SPI) for Flash only - stores boot FW and system
configuration data
• Intel Legacy Block (iLB) supports legacy PC platform features
— RTC, Interrupts, Timers, General Purpose I/Os (GPIO) and Peripheral interface
(LPC for TPM) blocks.
1.2.17
Package
This SoC is packaged in a Flip-Chip Ball Grid Array (FCBGA) package with 1170 solder
balls with 0.593 mm (minimum) ball pitch. The package dimensions are 25mm x
27mm. See Chapter 38, “Ballout and Package Information” for more details.
34
Intel® Atom™ Processor E3800 Product Family
Datasheet
Introduction
1.2.18
SKU List
Table 1.
Intel® Atom™ Processor E3800 Product Family SKUs
SKU
Processor
Number
CPU
TDP
(W)
Core
LFM (MHz)/
HFM (GHz)
Tj
(°C)
GFX
Normal / Burst
(MHz)
DDR
(MT/s)
Premium
E3845
4
10
500 / 1.91
-40 to 110
542 / 792
1333
Hi
E3827
2
8
500 / 1.75
-40 to 110
542 / 792
1333
Intermediate
E3826
2
7
533 / 1.46
-40 to 110
533 / 667
1066
Mid
E3825
2
6
533 / 1.33
-40 to 110
533 / NA
1066
Entry
E3815
1
5
533 / 1.46
-40 to 110
400 / NA
1066
Headless
E3805
2
3
533 / 1.33
-40 to 110
NA
1066
§
Intel® Atom™ Processor E3800 Product Family
Datasheet
35
Physical Interfaces
2
Physical Interfaces
Many interfaces contain physical pins. These groups of pins make up the physical
interfaces. Because of the large number of interfaces and the small size of the package,
Some interfaces share their pins with GPIOs, while others use dedicated physical pins.
This chapter summarizes the physical interfaces, including the diversity in GPIO
multiplexing options.
Figure 2.
Signals (1 of 2)
DRAM[1:0]_DQ[63:0]
DDI[1:0]_TXP/N[3:0]
Atom™
Cores
DRAM[1:0]_DQSP/N[7:0]
DRAM[1:0]_DM[7:0]
DDI[1:0]_AUXN
DDI[1:0]_AUXP
DRAM[1:0]_CS[2,0]#
DRAM[1:0]_CKP/N[2,0]
Direct
Display
Interface
DRAM[1:0]_CKE[2,0]
DRAM[1:0]_RAS#
DRAM[1:0]_CAS#
Display
DRAM[1:0]_ODT[2,0]
DRAM[1:0]_MA[15:00]
Dual Channel
DDR3L Memory
Interface
DDI[1:0]_DDCCLK
DDI[1:0]_DDCDATA
DDI[1:0]_HPD
DDI[1:0]_VDDEN
DDI[1:0]_BKLTEN
DDI[1:0]_BKLTCTL
VGA_R/G/B
VGA_HSYNC
DRAM[1:0]_WE#
DRAM[1:0]_BS[2:0]
VGA
DRAM[1:0]_DRAMRST#
VGA_VSYNC
VGA_DDCDATA
DRAM_CORE_PWROK
DRAM_VDD_S4_PWROK
VGA_DDCCLK
DRAM_VREF
TAP_TDI
TAP_TDO
MCSI1_DP/N[3:0]
MCSI1_CLKP/N
MCSI2_DP/N[0]
MCSI2_CLKP/N
MCSI3_CLKP/N
MIPI CSI
JTAG/Debug
Port
TAP_TMS
TAP_TCK
TAP_TRST#
TAP_PREQ#
MCSI_GPIO[11:00]
TAP_PRDY#
PROCHOT#
SVID_DATA
SVID_CLK
Processor
Power/Thermal
Integrated Clock
SVID_ALERT#
ICLK_OSCIN
ICLK_OSCOUT
Continued in Figure Below
36
Intel® Atom™ Processor E3800 Product Family
Datasheet
Physical Interfaces
Figure 3.
Signals (2 of 2)
Continued in Figure Above
HDA_SDO
HDA_SDI[1:0]
HDA_SYNC
Speaker
HD Audio
LPE_I2S2_DATAIN
LPE_I2S2_DATAOUT
LPE_I2S2_FRM
Legacy (ILB)
HDA_CLK
HDA_RST#
I2S
(LPE Audio)
LPC
ILB_LPC_AD[3:0]
ILB_LPC_FRAME#
ILB_LPC_CLK[1:0]
ILB_LPC_CLKRUN#
ILB_LPC_SERIRQ
RTC
LPE_I2S2_CLK
ILB_8254_SPKR
ILB_RTC_RST#
ILB_RTC_TEST#
ILB_RTC_EXTPAD
ILB_RTC_X1
ILB_RTC_X2
SIO_PWM[1:0]
SIO_SPI_MISO
SIO_SPI_MOSI
SIO_SPI_CS#
SIO_SPI_CLK
USB_OC[1:0]#
USB_PLL_MON
USB 2.0
(HSIC)
USB_HSIC[1:0]_DATA
USB_HSIC[1:0]_STROBE
SPI
USB 3.0
USB3_TXP/N
USB3_RXP/N
USB3_REXT
USB
PCIE_TXP/N[3:0]
PCIE_RXP/N[3:0]
PCIE_CLKREQ[3:0]#
USB 2.0
PWM
SIO_UART[2:1]_TXD
SIO_UART[2:1]_RXD
SIO_UART[2:1]_CTS#
SIO_UART[2:1]_RTS#
USB_DP/N[3:0]
I2C
Serial IO (SIO)
SIO_I2C[6:0]_CLK
SIO_I2C[6:0]_DATA
HSUART
USB 2.0
Device
(ULPI)
PCI Express
PCIE_CLKP/N[3:0]
USB 3.0
Device
SATA_TXP/N[1:0]
SATA_RXP/N[1:0]
SATA_GP[1:0]
SATA_LED#
MMC1_D[7:0]
MMC1_CMD
MMC1_CLK
USB3DEV_RXP/N
USB3DEV_REXT
PMC_PWRBTN#
PMC_RSMRST#
PMC_SLP_S3#
eMMC
Power
Management
Controller
(PMC)
SD/eMMC
SDIO
SD3_D[3:0]
SD3_CMD
GPIO_S5[30:22]
Intel® Atom™ Processor E3800 Product Family
Datasheet
Platform Control
GPIO
PMC_SLP_S4#
PMC_SUS_STAT#
PMC_SUSPWRDNACK
PMC_SUSCLK[0]
PMC_PLT_CLK[5:0]
PMC_CORE_PWROK
PMC_PLTRST#
PMC_BATLOW#
PMC_ACPRESENT
PMC_WAKE_PCIE[0]#
SD
GPIO_S0_SC[061:055]
GPIO_S0_SC[093:092]
GPIO_S5[10:00]
GPIO_S5[17]
USB3DEV_TXP/N
PMC_RSTBTN#
SD2_D[3:0]
SD3_CD#
SD3_WP
SD3_1P8EN
SD3_PWREN#
USB_ULPI_STP
USB_ULPI_CLK
USB_ULPI_RST#
USB_ULPI_REFCLK
SATA
MMC1_RST#
SD2_CMD
SD2_CLK
USB_ULPI_DATA[7:0]
USB_ULPI_DIR
USB_ULPI_NXT
PCU_SMB_DATA
SMBus
Boot SPI
PCU_SMB_CLK
PCU_SMB_ALERT#
PCU_SPI_MISO
PCU_SPI_MOSI
PCU_SPI_CS[1:0]#
PCU_SPI_CLK
37
Physical Interfaces
2.1
Pin States Through Reset
This chapter describes the states of each signal before, during and directly after reset.
Additionally, Some signals have internal pull-up/pull-down termination resistors, and
their values are also provided (Term). Termination tolerances are +/- 50% unless
otherwise specified by electrical specs (PCIe*, and other differential termination). All
signals with the “†” symbol are muxed and may not be available without configuration.
See Section 2.30, “Configurable IO: GPIO Muxing” on page 62.
Note:
The internal termination resistor values & pull directions described in this
chapter are the power-on defaults. Firmware & software may change the
termination value, pull direction or disable the termination completely, on a
pin-by-pin basis, using the _PCONF0 register corresponding to that pin.
Table 2.
Platform Power Well Definitions
Power Type
38
Power Well Description
V1P05S
1.05 V rail. On in S0 only.
V1P0A
1.0 V rail. On in S0 through S4/5.
V1P0S
1.0 V rail. On in S0 only.
V1P24A
1.24 V rail. On in S0 through S4/5.
V1P24S
1.24 V rail. On in S0 only.
V1P35U
1.35 V rail. On in S0 through S3.
V1P8A
1.8 V rail. On in S0 through S4/5.
V1P35S
1.35 V rail. On in S0 only.
V1P8S
1.8 V rail. On in S0 only.
V3P3A
3.3 V rail. On in S0 through S4/5.
VAUD
1.5 V rail for HD Audio. 1.8 V rail for I2S. On in S0 only.
VCC
Variable core rail. On in S0 only.
VLPC
1.8 or 3.3 V rail for LPC. On in S0 only.
VNN
Variable rail. On in S0 only.
VPCIESATA
1.0 V rail for PCIe* and SATA. On in S0 only.
VRTC
RTC voltage rail. On in S0 through G3.
VSDIO
1.8 or 3.3 V rail for SD3. On in S0 only.
VSFR
1.35 V rail for internal PLLs. On in S0 only.
VUSB2
3.3 V rail. On in S0 through S4/5.
VVGA_GPIO
3.3 V rail for VGA sideband. On in S0 only.
Intel® Atom™ Processor E3800 Product Family
Datasheet
Physical Interfaces
Table 3.
Default Buffer State Definitions
Buffer State
2.2
Description
High-Z
The SoC places this output in a high-impedance state. For inputs, external
drivers are not expected.
Do Not Care
The state of the input (driven or tristated) does not affect the SoC. For outputs,
it is assumed that the output buffer is in a high-impedance state.
VOH
The SoC drives this signal high with a termination of 50 Ω.
VOL
The SoC drives this signal low with a termination of 50 Ω.
Unknown
The SoC drives or expects an indeterminate value.
VIH
The SoC expects/requires the signal to be driven high.
VIL
The SoC expects/requires the signal to be driven low.
Pull-up
This signal is pulled high by a pull-up resistor (internal value specified in “Term”
column).
Pull-down
This signal is pulled low by a pull-down resistor (internal value specified in
“Term” column).
Running/T
The clock is toggling, or the signal is transitioning.
Off
The power plane for this signal is powered down. The SoC does not drive
outputs, and inputs should not be driven to the SoC. (VSS on output)
System Memory Controller Interface Signals
See Chapter 12, “System Memory Controller” for more details.
Note:
S0ix is not supported for Bay Trail-M/D SKUs and Bay Trail-I SKUs.
Intel® Atom™ Processor E3800 Product Family
Datasheet
39
Physical Interfaces
Table 4.
DDR3L System Memory Signals
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
DRAM0_CKP[2,0]
O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM0_CKN[2,0]
O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM0_CS#[2,0]
O
-
V1P35U
Off
VOH
VOH
VOH
DRAM0_CKE[2,0]
O
-
V1P35U
Off
VOL
VOL
VOL
DRAM0_CAS#
O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM0_RAS#
O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM0_WE#
O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM0_BS[2:0]
O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM0_DRAMRST#
O
-
V1P35U
Off
-
-
-
DRAM0_ODT[2,0]
O
-
V1P35U
Off
VOL
VOL
VOL
DRAM0_DQ[63:0]
I/O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM0_DM[7:0]
O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM0_DQSP[7:0]
I/O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM0_DQSN[7:0]
I/O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM1_CKP[2,0]
O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM1_CKN[2,0]
O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM1_CKE[2,0]
O
-
V1P35U
Off
VOL
VOL
VOL
DRAM1_CS#[2,0]
O
-
V1P35U
Off
VOH
VOH
VOH
Signal Name
DRAM1_CAS#
O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM1_RAS#
O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM1_WE#
O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM1_BS[2:0]
O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM1_DRAMRST#
O
-
V1P35U
Off
-
-
-
DRAM1_ODT[2,0]
O
-
V1P35U
Off
VOL
VOL
VOL
DRAM1_DQ[63:0]
I/O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM1_DM[7:0]
O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM1_DQSP[7:0]
I/O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM1_DQSN[7:0]
I/O
-
V1P35U
Off
High-Z
High-Z
High-Z
DRAM_VDD_S4_PWROK
I
-
V1P35U
VIL
VIH
Unknown
VIH
DRAM_CORE_PWROK
I
-
V1P35U
VIL
VIL
Unknown
VIH
DRAM_VREF
I
-
V1P35U
DRAM_RCOMP[2:0]
-
-
V1P35U
40
Notes
Intel® Atom™ Processor E3800 Product Family
Datasheet
Physical Interfaces
2.3
PCI Express* 2.0 Interface Signals
See Chapter 23, “PCI Express* 2.0” for more details.
Note:
S0ix is not supported for Bay Trail-M/D SKUs and Bay Trail-I SKUs.
Table 5.
PCI Express* 2.0 Interface Signals
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
PCIE_TXP[3:0]
O
50
VPCIESATA
Off
Off
VOL
VOL
PCIE_TXN[3:0]
O
50
VPCIESATA
Off
Off
VOL
VOL
Signal Name
PCIE_RXP[3:0]
I
50
VPCIESATA
Off
Off
High-Z
High-Z
PCIE_RXN[3:0]
I
50
VPCIESATA
Off
Off
High-Z
High-Z
PCIE_CLKP[3:0]
O
-
V1P0S
Off
Off
Running/
VIL
Running/
VIL
PCIE_CLKN[3:0]
O
-
V1P0S
Off
Off
Running/
VIL
Running/
VIL
PCIE_CLKREQ[3:0]#†
I
20k(H)
V1P8S
Off
Off
Pull_up
Pull_up
PCIE_RCOMP_P/N
-
-
Notes
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.
2.4
USB 2.0 Host (EHCI/xHCI) Interface Signals
See Chapter 18, “USB Host Controller Interfaces (xHCI, EHCI)” for more details.
Note:
S0ix is not supported for Bay Trail-M/D SKUs and Bay Trail-I SKUs.
Table 6.
USB 2.0 Interface Signals
Default Buffer State
Dir
Term
Plat.
Power
USB_DN[3:0]
I/O
-
VUSB2
USB_DP[3:0]
I/O
-
VUSB2
USB_OC[1:0]#†
I
20k(H)
V1P8A
USB_RCOMPI
I
-
-
USB_RCOMPO
O
-
-
Signal Name
S4/S5
S3
Reset
Enter S0
Pull-up
Pull-up
Pull-up
Pull-up
Notes
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.
Intel® Atom™ Processor E3800 Product Family
Datasheet
41
Physical Interfaces
2.5
USB 2.0 HSIC Interface Signals
See Chapter 18, “USB Host Controller Interfaces (xHCI, EHCI)” for more details.
Note:
S0ix is not supported for Bay Trail-M/D SKUs and Bay Trail-I SKUs.
Table 7.
USB 2.0 HSIC Interface Signals
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
USB_HSIC0_DATA
I/O
-
V1P24A
Running
Running
VOH
Running
USB_HSIC0_STROBE
I/O
-
V1P24A
VOH
Signal Name
USB_HSIC1_DATA
I/O
-
V1P24A
USB_HSIC1_STROBE
I/O
-
V1P24A
I
-
V1P24A
USB_HSIC_RCOMP
2.6
Notes
VOH
VOH
VOH
USB 3.0 (xHCI) Host Interface Signals
Note:
S0ix is not supported for Bay Trail-M/D SKUs and Bay Trail-I SKUs.
Table 8.
USB 3.0 Interface Signals
Default Buffer State
Dir
Term
Plat.
Power
USB3_TXN[0]
O
-
V1P0A
USB3_TXP[0]
O
-
V1P0A
USB3_RXN[0]
I
-
V1P0A
Signal Name
USB3_RXP[0]
I
-
V1P0A
USB3_REXT[0]
I
-
V1P0A
2.7
S4/S5
S3
Reset
Enter S0
VOL
VOL
VOH
VOH
Notes
USB 2.0 Device (ULPI) Interface Signals
See Chapter 19, “USB Device Controller Interfaces (3.0, ULPI)” for more details.
Note:
42
S0ix is not supported for Bay Trail-I SKUs.
Intel® Atom™ Processor E3800 Product Family
Datasheet
Physical Interfaces
Table 9.
USB 2.0 Device Interface Signals
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
Notes
I
20k(L)
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
I/O
20k(L)
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
USB_ULPI_DIR†
I
20k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
USB_ULPI_NXT†
I
20k(L)
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
USB_ULPI_STP†
O
20k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
USB_ULPI_REFCLK†
O
20k(L)
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
USB_ULPI_RST#†
O
-
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Signal Name
USB_ULPI_CLK†
USB_ULPI_DATA[0:7]†
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.
2.8
USB 3.0 Device Interface Signals
See Chapter 19, “USB Device Controller Interfaces (3.0, ULPI)” for more details.
Note:
S0ix is not supported for Bay Trail-I SKUs.
Table 10.
USB 3.0 Device Interface Signals
Default Buffer State
Dir
Term
Plat.
Power
USB3DEV_TXN[0]
O
-
V1P0S
USB3DEV_TXP[0]
O
-
V1P0S
USB3DEV_RXN[0]
I
-
V1P0S
USB3DEV_RXP[0]
I
-
V1P0S
USB3DEV_REXT[0]
I
-
V1P0S
Signal Name
Intel® Atom™ Processor E3800 Product Family
Datasheet
S4/S5
S3
Reset
Enter S0
Notes
43
Physical Interfaces
2.9
Serial ATA (SATA) 2.0 Interface Signals
See Chapter 17, “Serial ATA (SATA)” for more details.
Note:
S0ix is not supported for Bay Trail-M/D SKUs and Bay Trail-I SKUs.
Table 11.
SATA 2.0 Interface Signals
Default Buffer State
Signal Name
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
Notes
SATA_TXP[1:0]
O
VPCIESATA
Off
Off
SATA_TXN[1:0]
O
VPCIESATA
Off
Off
SATA_RXP[1:0]
I
VPCIESATA
Off
Off
SATA_RXN[1:0]
I
VPCIESATA
Off
Off
SATA_LED#†
O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
Pull-up
SATA_GP[1:0]†
I
20k(L)
V1P8S
Off
Off
Pull-down
Pull-down
Pull-down
SATA_RCOMP_P/N
-
-
1.0 V
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.
2.10
Integrated Clock Interface Signals
See Chapter 5, “Integrated Clock” for more details..
Table 12.
Integrated Clock Interface Signals
Default Buffer State
Plat.
Power
S4/S5
S3
Reset
Enter S0
-
Off
Off
Running
Running
O
-
Off
Off
Running
Running
-
-
Off
Off
ICLK_RCOMP
-
-
Off
Off
ICLK_DRAM_TERM[1:0]
-
-
-
Pull-down
Pull-down
Pull-down
Pull-down
ICLK_USB_TERM[1:0]
-
-
-
Pull-down
Pull-down
Pull-down
Pull-down
Signal Name
Dir
Term
ICLK_OSCIN
I
ICLK_OSCOUT
ICLK_ICOMP
44
Notes
Intel® Atom™ Processor E3800 Product Family
Datasheet
Physical Interfaces
2.11
Display - Digital Display Interface (DDI) Signals
See Chapter 14, “Graphics, Video and Display” for more details.
Note:
S0ix is not supported for Bay Trail-M/D SKUs and Bay Trail-I SKUs.
Table 13.
Digital Display Interface Signals
Default Buffer State
Signal Name
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
DDI0_TXP[3:0]
O
V1P0S
Off
Off
DDI0_TXN[3:0]
O
V1P0S
Off
Off
DDI0_AUXP
I/O
V1P0S
Off
Off
DDI0_AUXN
I/O
V1P0S
Off
Off
DDI0_BKLTCTL†
I/O
20k(L)
V1P8S
Off
Off
Pull-down
Pull-down
DDI0_BKLTEN†
I/O
20k(L)
V1P8S
Off
Off
Pull-down
Pull-down
DDI0_DDCCLK†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
DDI0_DDCDATA†
I/O
20k(L)
V1P8S
Off
Off
Pull-down1
Pull-up2
1
DDI0_HPD†
I/O
20k(L)
V1P8S
Off
Off
Pull-down
Pull-down
DDI0_VDDEN†
I/O
20k(L)
V1P8S
Off
Off
Pull-down
Pull-down
DDI_RCOMP_P/N
-
-
V1P0S
DDI1_TXP[3:0]
O
V1P0S
Off
Off
DDI1_TXN[3:0]
O
V1P0S
Off
Off
DDI1_AUXP
I/O
V1P0S
Off
Off
DDI1_AUXN
I/O
V1P0S
Off
Off
DDI1_BKLTCTL†
I/O
V1P8S
Off
Off
Pull-down
Pull-down
20k(L)
DDI1_BKLTEN†
I/O
20k(L)
V1P8S
Off
Off
Pull-down
Pull-down
DDI1_DDCCLK†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
1
Pull-up2
DDI1_DDCDATA†
I/O
20k(L)
V1P8S
Off
Off
Pull-down
DDI1_HPD†
I/O
20k(L)
V1P8S
Off
Off
Pull-down
Pull-down
DDI1_VDDEN†
I/O
20k(L)
V1P8S
Off
Off
Pull-down
Pull-down
1
Notes
NOTE: 1. The internal pull-down resistor is disabled upon assertion of PMC_CORE_PWROK.
NOTE: 2. When the corresponding DDI port is used, an external pull-up resistor is required.
NOTE: 3. All signals with the “†” symbol are muxed and may not be available without configuration.
Intel® Atom™ Processor E3800 Product Family
Datasheet
45
Physical Interfaces
2.12
Display – VGA Interface Signals
See Chapter 14, “Graphics, Video and Display” for more details.
Note:
S0ix is not supported for Bay Trail-M/D SKUs and Bay Trail-I SKUs.
Table 14.
VGA Interface Signals
Default Buffer State
Signal Name
Dir
Plat.
Power
Term
Type
S4/S5
S3
Reset
VGA_RED
O
VVGA_GPIO
Off
Off
High-Z
VGA_GREEN
O
VVGA_GPIO
Off
Off
High-Z
VGA_BLUE
O
VVGA_GPIO
Off
Off
High-Z
VGA_IREF
Off
Off
VOL
VGA_IRTN
Off
Off
High-Z
Off
Off
VOL
VGA_HSYNC
O
VVGA_GPIO
VGA_VSYNC
O
VVGA_GPIO
Off
Off
VOL
VGA_DDCCLK
O
VVGA_GPIO
Off
Off
High-Z
I/O
VVGA_GPIO
Off
Off
High-Z
VGA_DDCDATA
2.13
Enter
S0
Notes
MIPI Camera Serial Interface (CSI) and ISP
Interface Signals
See Chapter 15, “MIPI-Camera Serial Interface (CSI) and ISP” for more details.
Note:
S0ix is not supported for Bay Trail-I SKUs.
Table 15.
MIPI CSI Interface Signals (Sheet 1 of 2)
Default Buffer State
Signal Name
Dir
Term
Plat.
Power
S4/S5
MCSI1_CLKN
I
V1P24S
Off
MCSI1_CLKP
I
V1P24S
Off
MCSI1_DN[0:3]
I
V1P24S
Off
MCSI1_DP[0:3]
I
V1P24S
Off
MCSI2_CLKN
I
V1P24S
Off
MCSI2_CLKP
I
V1P24S
Off
MCSI2_DN[0]
I
V1P24S
Off
MCSI2_DP[0]
I
V1P24S
Off
46
S3
Reset
Enter S0
Notes
Intel® Atom™ Processor E3800 Product Family
Datasheet
Physical Interfaces
Table 15.
MIPI CSI Interface Signals (Sheet 2 of 2)
Default Buffer State
Signal Name
Dir
Term
Plat.
Power
S4/S5
MCSI3_CLKN
I
V1P24S
Off
MCSI3_CLKP
I
V1P24S
Off
MCSI_RCOMP
-
V1P24S
Off
2.14
S3
Reset
Enter S0
High-Z
High-Z
High-Z
Notes
Intel® High Definition Audio Interface Signals
See Chapter 20, “Intel® High Definition Audio” for more details.
Note:
S0ix is not supported for Bay Trail-M/D SKUs and Bay Trail-I SKUs.
Table 16.
HD Audio Interface Signals
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
HDA_SDO†
O
20k(L)
VAUD
Off
Off
Pull-down
Pull-down
HDA_SDI[1:0]†
I
20k(L)
VAUD
Off
Off
Pull-down
Pull-down
HDA_CLK†
O
20k(L)
VAUD
Off
Off
Pull-down
Pull-down
HDA_RST#†
O
20k(L)
VAUD
Off
Off
Pull-down
Pull-down
HDA_SYNC†
O
20k(L)
VAUD
Off
Off
Pull-down
Pull-down
HDA_LPE_RCOMP
-
Signal Name
Notes
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.
2.15
Low Power Engine (LPE) for Audio (I2S) Interface
Signals
See Chapter 21, “Low Power Engine (LPE) for Audio (I2S)” for more details.
Note:
S0ix is not supported for Bay Trail-I SKUs.
Intel® Atom™ Processor E3800 Product Family
Datasheet
47
Physical Interfaces
Table 17.
LPE Interface Signals
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
LPE_I2S[2:0]_CLK
I/O
20k(L)
V1P8S
Off
Off
Pull-down
Pull-down
LPE_I2S[2:0]_FRM
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
LPE_I2S[2:0]_DATAOUT
O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
LPE_I2S[2:0]_DATAIN
I
20k(L)
V1P8S
Off
Off
Pull-down
Pull-down
Signal Name
2.16
Notes
Storage Control Cluster (eMMC, SDIO, SD)
Interface Signals
See Chapter 16, “Storage Control Cluster (eMMC, SDIO, SD Card)” for more details.
Note:
S0ix is not supported for Bay Trail-M/D SKUs and Bay Trail-I SKUs.
Table 18.
Storage Control Cluster (eMMC, SDIO, SD) Interface Signals (Sheet 1 of 2)
Default Buffer State
Signal Name
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
MMC1_D[7:0]†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
MMC1_CMD†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
MMC1_CLK†
I/O
20k(L)
V1P8S
Off
Off
Pull-down
Pull-down
MMC1_RST#†
I/O
20k(L)
V1P8S
Off
Off
Pull-down
Pull-down
MMC1_RCOMP
I/O
-
V1P8S
SD2_D[3:0]†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SD2_CMD†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SD2_CLK†
I/O
20k(L)
V1P8S
Off
Off
Pull-down
Pull-down
SD3_D[3:0]†
I/O
20k(H)
VSDIO
Off
Off
Pull-up
Pull-up
SD3_CMD†
I/O
20k(H)
VSDIO
Off
Off
Pull-up
Pull-up
SD3_CLK†
I/O
20k(L)
VSDIO
Off
Off
Pull-down
Pull-down
O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SD3_CD#†
I
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SD3_1P8EN†
O
20k(L)
V1P8S
Off
Off
Pull-down
Pull-down
SD3_PWREN#†
48
Notes
Intel® Atom™ Processor E3800 Product Family
Datasheet
Physical Interfaces
Table 18.
Storage Control Cluster (eMMC, SDIO, SD) Interface Signals (Sheet 2 of 2)
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
SD3_WP†
I
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SD3_RCOMP
-
-
VSDIO
Signal Name
Notes
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.
NOTE: VSDIO voltage selection is controlled by SD3_1P8EN. 3.3V is default due to pull-down. VSDIO can be
either 1.8 or 3.3 V when these VSDIO referenced signals are configured to be GPIO’s to meet different
platform requirements.
2.17
SIO – High Speed UART Interface Signals
See Chapter 27, “SIO – High Speed UART” for more details.
Note:
S0ix is not supported for Bay Trail-M/D SKUs and Bay Trail-I SKUs.
Table 19.
High Speed UART Interface Signals
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
SIO_UART1_RXD†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_UART1_TXD†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
Signal Name
SIO_UART1_RTS#†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_UART1_CTS#†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_UART2_RXD†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_UART2_TXD†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_UART2_RTS#†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_UART2_CTS#†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
Notes
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.
Intel® Atom™ Processor E3800 Product Family
Datasheet
49
Physical Interfaces
2.18
SIO – I2C Interface Signals
See Chapter 26, “SIO - I2C Interface” for more details.
Note:
S0ix is not supported for Bay Trail-M/D SKUs and Bay Trail-I SKUs.
Table 20.
SIO - I2C Interface Signals
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
SIO_I2C0_DATA†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_I2C0_CLK†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_I2C1_DATA†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_I2C1_CLK†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_I2C2_DATA†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_I2C2_CLK†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_I2C3_DATA†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_I2C3_CLK†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_I2C4_DATA†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_I2C4_CLK†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_I2C5_DATA†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_I2C5_CLK†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_I2C6_DATA†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_I2C6_CLK†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
Signal Name
Notes
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.
2.19
SIO – Serial Peripheral Interface (SPI) Signals
See Chapter 25, “SIO – Serial Peripheral Interface (SPI)” for more details.
Note:
S0ix is not supported for Bay Trail-M/D SKUs and Bay Trail-I SKUs.
Table 21.
SIO - Serial Peripheral Interface (SPI) Signals (Sheet 1 of 2)
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
SIO_SPI_CLK†
I/O
20k(L)
V1P8S
Off
Off
Pull-down
Pull-down
SIO_SPI_CS#†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
Signal Name
50
Notes
Intel® Atom™ Processor E3800 Product Family
Datasheet
Physical Interfaces
Table 21.
SIO - Serial Peripheral Interface (SPI) Signals (Sheet 2 of 2)
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
SIO_SPI_MOSI†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
SIO_SPI_MISO†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
Signal Name
Notes
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.
2.20
PCU – iLB – Real Time Clock (RTC) Interface
Signals
See Chapter 36, “PCU – iLB – Real Time Clock (RTC)” for more details.
Note:
S0ix is not supported for Bay Trail-M/D SKUs and Bay Trail-I SKUs.
Table 22.
PCU - iLB - Real Time Clock (RTC) Interface Signals
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
ILB_RTC_X1
I
-
VRTC
Running
Running
Running
Running
ILB_RTC_X2
O
-
VRTC
Running
Running
Running
Running
ILB_RTC_RST#
I
-
VRTC
VIH
VIH
VIH
VIH
ILB_RTC_TEST#
I
-
VRTC
VIH
VIH
VIH
VIH
ILB_RTC_EXTPAD
O
-
VRTC
Signal Name
2.21
Notes
PCU – iLB – Low Pin Count (LPC) Bridge Interface
Signals
See Chapter 35, “PCU – iLB – Low Pin Count (LPC) Bridge” for more details.
Note:
S0ix is not supported for Bay Trail-M/D SKUs and Bay Trail-I SKUs.
Note:
If the VGA interface is used, VLPC must have a nominal voltage of 3.3V.
Intel® Atom™ Processor E3800 Product Family
Datasheet
51
Physical Interfaces
Table 23.
PCU - iLB - LPC Bridge Interface Signals
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
ILB_LPC_AD[3:0]†
I/O
20k(H)
VLPC
Off
Off
Pull-up
Running
ILB_LPC_FRAME#†
I/O
20k(H)
VLPC
Off
Off
VOH
Running
Signal Name
ILB_LPC_SERIRQ†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Running
ILB_LPC_CLKRUN#†
I/O
20k(H)
VLPC
Off
Off
Pull-up
Running
ILB_LPC_CLK[1:0]†
I/O
20k(L)
VLPC
Off
Off
VOL
Running
LPC_RCOMP
-
Notes
VLPC
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.
2.22
PCU – Serial Peripheral Interface (SPI) Signals
See Chapter 31, “PCU – Serial Peripheral Interface (SPI)” for more details.
Note:
S0ix is not supported for Bay Trail-M/D SKUs and Bay Trail-I SKUs.
Table 24.
PCU - Serial Peripheral Interface (SPI) Signals
Default Buffer State
Signal Name
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter
S0
PCU_SPI_CLK
O
20k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Running
PCU_SPI_CS[0]#
O
20k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Running
PCU_SPI_CS[1]#†
O
20k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Running
PCU_SPI_MOSI
I/O
20k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
PCU_SPI_MISO
I
20k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
Notes
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.
52
Intel® Atom™ Processor E3800 Product Family
Datasheet
Physical Interfaces
2.23
PCU – System Management Bus (SMBus)
Interface Signals
See Chapter 33, “PCU – System Management Bus (SMBus)” for more details.
Note:
S0ix is not supported for Bay Trail-M/D SKUs and Bay Trail-I SKUs.
Table 25.
PCU - System Management Bus (SMBus) Interface Signals
Default Buffer State
Signal Name
PCU_SMB_CLK†
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
PCU_SMB_DATA†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
PCU_SMB_ALERT#†
I/O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
2.24
PCU – Power Management Controller (PMC)
Interface Signals
See Chapter 30, “PCU – Power Management Controller (PMC)” for more details.
Note:
S0ix is not supported for Bay Trail-M/D SKUs and Bay Trail-I SKUs.
Table 26.
PCU - Power Management Controller (PMC) Interface Signals (Sheet 1 of 2)
Default Buffer State
Signal Name
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
PMC_PLTRST#
O
-
V1P8A
VOL
VOL
VOL->VOH
VOH
PMC_PWRBTN#†
I
20k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
PMC_RSTBTN#
I
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
PMC_SUSPWRDNACK†
O
-
V1P8A
VOH/VOL
VOH/VOL
VOH/VOL
VOH/VOL
PMC_SUS_STAT#†
O
-
V1P8A
VOL
VOL
VOL
VOH
PMC_SUSCLK[0]†
O
-
V1P8A
Running
Running
Running
Running
PMC_SUSCLK[3:1]†
O
-
PMC_SLP_S3#
O
-
V1P8A
VOL
VOL
VOH
VOH
PMC_SLP_S4#
O
-
V1P8A
VOL
VOH
VOH
VOH
PMC_WAKE_PCIE[0]#
I
20k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
PMC_WAKE_PCIE[3:1]#†
I
20k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
PMC_ACPRESENT
I
20k(L)
V1P8A
High-Z
Pull-down
Pull-down
Pull-down
PMC_BATLOW#
I
20k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
Intel® Atom™ Processor E3800 Product Family
Datasheet
Notes
53
Physical Interfaces
Table 26.
PCU - Power Management Controller (PMC) Interface Signals (Sheet 2 of 2)
Default Buffer State
Signal Name
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
PMC_CORE_PWROK
I
VRTC
VIL
VIL
VIL
VIH
PMC_RSMRST#
I
VRTC
VIH
VIH
VIH
VIH
Notes
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.
2.25
JTAG and Debug Interface Signals
Note:
S0ix is not supported for Bay Trail-M/D SKUs and Bay Trail-I SKUs.
Table 27.
JTAG and Debug Interface Signals
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
TAP_TCK
I
2k(L)
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
TAP_TDI
I
2k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
TAP_TDO
O
-
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
Signal Name
TAP_TMS
I
2k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
TAP_TRST#
I
2k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
TAP_PRDY#
O
2k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
TAP_PREQ#
I
2k(H)
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
2.26
Table 28.
Notes
Miscellaneous Signals
Miscellaneous Signals and Clocks (Sheet 1 of 2)
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
I/O
2k(H)
V1P0S
Off
Off
Pull-up
Pull-up
SVID_CLK
O
2k(H)
V1P0S
Off
Off
Pull-up
Pull-up
SVID_ALERT#
I
2k(H)
V1P0S
Off
Off
Pull-up
Pull-up
Signal Name
SVID_DATA
PROCHOT#
I/O
2k(H)
V1P0S
Off
Off
Pull-up
Pull-up
ILB_8254_SPKR†
O
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
ILB_NMI†
I
20k(H)
V1P8S
Off
Off
Pull-up
Pull-up
54
Intel® Atom™ Processor E3800 Product Family
Datasheet
Physical Interfaces
Table 28.
Miscellaneous Signals and Clocks (Sheet 2 of 2)
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
PMC_PLT_CLK[5:0]†
O
20k(L)
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_RCOMP
-
-
V1P8S
Off
Off
Active
Active
Signal Name
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.
NOTE:GPIO_RCOMP provides compensation for the following pins: GPIO_S5[10],
PMC_SUSPWRDNACK PMC_SUSCLK[0], GPIO_S5[13], PMC_SLP_S4#, PMC_SLP_S3#,
USB_ULPI_RST#, PMC_ACPRESENT, PMC_WAKE_PCIE[0]#, PMC_BATLOW#,
PMC_PWRBTN#, PMC_PLTRST#, GPIO_S5[17], PMC_SUS_STAT#, USB_OC[1:0]#,
GPIO_S5[09:00], GPIO_S5[30:22], TAP_TCK TAP_TRST#, TAP_TMS, TAP_TDI, TAP_TDO,
TAP_PRDY#, TAP_PREQ#
2.27
GPIO Signals
Most GPIO’s are configurable via multiplexors. See “Chapter 10, “Ballout and Package
Information” for configuration options with the interfaces presented in this chapter.
Table 29.
GPIO Signals (Sheet 1 of 5)
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
GPIO_S0_SC[000]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[001]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[002]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[003]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[004]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[005]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[006]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[007]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[008]†
I/O
20k,L
VAUD
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[009]†
I/O
20k,L
VAUD
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[010]†
I/O
20k,L
VAUD
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[011]†
I/O
20k,L
VAUD
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[012]†
I/O
20k,L
VAUD
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[013]†
I/O
20k,L
VAUD
Off
Off
Pull-down
Pull-down
Signal Name
GPIO_S0_SC[014]†
I/O
20k,L
VAUD
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[015]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[016]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[017]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
Intel® Atom™ Processor E3800 Product Family
Datasheet
55
Physical Interfaces
Table 29.
GPIO Signals (Sheet 2 of 5)
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
GPIO_S0_SC[018]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[019]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[020]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[021]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[022]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[023]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[024]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[025]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[026]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[027]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[028]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[029]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[030]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[031]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[032]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[033]†
I/O
20k,L
VSDIO
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[034]†
I/O
20k,H
VSDIO
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[035]†
I/O
20k,H
VSDIO
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[036]†
I/O
20k,H
VSDIO
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[037]†
I/O
20k,H
VSDIO
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[038]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[039]†
I/O
20k,H
VSDIO
Off
Off
Pull-up
Pull-up
Signal Name
GPIO_S0_SC[040]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[041]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[042]†
I/O
20k,H
VLPC
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[043]†
I/O
20k,H
VLPC
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[044]†
I/O
20k,H
VLPC
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[045]†
I/O
20k,H
VLPC
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[046]†
I/O
20k,H
VLPC
Off
Off
1
1
GPIO_S0_SC[047]†
I/O
20k,L
VLPC
Off
Off
0
0
GPIO_S0_SC[048]†
I/O
20k,L
VLPC
Off
Off
0
0
GPIO_S0_SC[049]†
I/O
20k,H
VLPC
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[050]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[051]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[052]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
56
Intel® Atom™ Processor E3800 Product Family
Datasheet
Physical Interfaces
Table 29.
GPIO Signals (Sheet 3 of 5)
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
GPIO_S0_SC[053]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[054]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[055]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[056]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[057]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[058]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[059]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[060]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[061]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[062]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[063]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[064]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[065]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[066]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[067]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[068]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[069]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[070]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[071]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[072]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[073]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[074]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[075]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[076]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[077]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[078]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[079]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[080]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[081]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[082]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[083]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[084]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[085]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[086]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[087]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
Signal Name
Intel® Atom™ Processor E3800 Product Family
Datasheet
57
Physical Interfaces
Table 29.
GPIO Signals (Sheet 4 of 5)
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
GPIO_S0_SC[088]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[089]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[090]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[091]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[092]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[093]†
I/O
20k,H
V1P8S
Off
Off
Pull-up
Pull-up
GPIO_S0_SC[094]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[095]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[096]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[097]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[098]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[099]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[100]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S0_SC[101]†
I/O
20k,L
V1P8S
Off
Off
Pull-down
Pull-down
GPIO_S5[00]†
I/O
20k,H
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
GPIO_S5[01]†
I/O
20k,H
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
GPIO_S5[02]†
I/O
20k,H
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
GPIO_S5[03]†
I/O
20k,H
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
GPIO_S5[04]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[05]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[06]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[07]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[08]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[09]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[10]†
I/O
20k,H
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
GPIO_S5[11]†
I/O
-
V1P8A
0/1
0/1
0
0/1
GPIO_S5[12]†
I/O
-
V1P8A
T
T
T
T
GPIO_S5[13]†
I/O
-
V1P8A
0
0
0
0/1
GPIO_S5[14]†
I/O
-
V1P8A
0
0
0
0/1
GPIO_S5[15]†
I/O
20k,H
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
GPIO_S5[16]†
I/O
20k,H
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
GPIO_S5[17]†
I/O
20k,H
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
GPIO_S5[18]†
I/O
-
V1P8A
0
0
0
1
GPIO_S5[19]†
I/O
20k,H
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
GPIO_S5[20]†
I/O
20k,H
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
Signal Name
58
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Datasheet
Physical Interfaces
Table 29.
GPIO Signals (Sheet 5 of 5)
Default Buffer State
Dir
Term
Plat.
Power
S4/S5
S3
Reset
Enter S0
GPIO_S5[21]†
I/O
20k,H
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
GPIO_S5[22]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[23]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[24]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[25]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[26]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[27]†
I/O
20k,H
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
GPIO_S5[28]†
I/O
20k,H
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
GPIO_S5[29]†
I/O
20k,H
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
GPIO_S5[30]†
I/O
20k,H
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
GPIO_S5[31]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[32]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[33]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[34]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[35]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[36]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[37]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[38]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[39]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[40]†
I/O
20k,H
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
GPIO_S5[41]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
GPIO_S5[42]†
I/O
20k,H
V1P8A
Pull-up
Pull-up
Pull-up
Pull-up
GPIO_S5[43]†
I/O
20k,L
V1P8A
Pull-down
Pull-down
Pull-down
Pull-down
Signal Name
2.28
Power And Ground Pins
Power Rail Ball Name Format: [Function]_[Voltage]_[S-State]{_[Filter]}:
• [Function]: The SoC function associated with the power rail.
— E.g CORE, USB, …
• [Voltage]: The nominal voltage associated with the power rail.
— E.g. 1P05, 3P3, VCC, …
• [S-State]: The ACPI system state, from S0 to G3, when the this rail is turned off.
• [Filter]: An optional indicator that one or more power rail balls have unique filtering
requirements or requirement to be uniquely identified.
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59
Physical Interfaces
Note:
Table 30.
The Resume power well is a set of supply rails (where [S-State] = G3) that must be
powered even when S3/4/5 states aren’t used. The “Resume Well” is also referred to as
the “Suspend Power Well”, “Always on/SUS”, “SUS power”, or “SUS well”.
Power and Ground Pins (Sheet 1 of 2)
Power Rails
CORE_V1P05_S3
CORE_VCC_S3
Platform
Power
Nominal
Voltages
First Off State
V1P05S
1.05 V
S3
VCC
Variable
S3
See CORE_VCC_S3
CORE_VCC_SENSE
-
-
-
DDI_V1P0_S3
V1P0S
1.0 V
S3
DRAM_V1P0_S3
V1P0S
1.0 V
S3
VSFR
1.35 V
S3
DRAM_VDD_S4
V1P35U
1.35 V
S4
GPIO_V1P0_S3
V1P0S
1.0 V
S3
HDA_LPE_V1P5V1P8_S3
VAUD
1.5/1.8 V
S3
ICLK_V1P35_S3_F1
VSFR
1.35 V
S3
ICLK_V1P35_S3_F2
VSFR
1.35 V
S3
LPC_V1P8V3P3_S3
VLPC
1.8/3.3 V
S3
V1P24S
1.24 V
S3
V1P8S
1.8 V
S3
PCIE_SATA_V1P0_S3
VPCIESATA
1.0 V
S3
PCIE_V1P0_S3
VPCIESATA
1.0 V
S3
PCU_V1P8_G3
V1P8A
1.8 V
G3
PCU_V3P3_G3
V3P3A
3.3 V
G3
PMC_V1P8_G3
V1P8A
1.8 V
G3
VRTC
2.0-3.0 at
SoC
CORE_VSS_SENSE
DRAM_V1P35_S3_F1
MIPI_V1P24_S3
MIPI_V1P8_S3
RTC_VCC
(normally battery backed)
VPCIESATA
1.0 V
S3
SD3_V1P8V3P3_S3
VSDIO
1.8/3.3 V
S3
SVID_V1P0_S3
V1P0S
1.0 V
S3
UNCORE_V1P0_G3
V1P0A
1.0 V
G3
UNCORE_V1P0_S3
SATA_V1P0_S3
60
V3P3A(pre
diode drop)
V1P0S
1.0 V
S3
UNCORE_V1P35_S3_F1
VSFR
1.35 V
S3
UNCORE_V1P35_S3_F2
VSFR
1.35 V
S3
UNCORE_V1P35_S3_F3
VSFR
1.35 V
S3
Intel® Atom™ Processor E3800 Product Family
Datasheet
Physical Interfaces
Table 30.
Power and Ground Pins (Sheet 2 of 2)
Power Rails
Platform
Power
Nominal
Voltages
First Off State
UNCORE_V1P35_S3_F4
VSFR
1.35 V
S3
UNCORE_V1P35_S3_F5
VSFR
1.35 V
S3
UNCORE_V1P35_S3_F6
VSFR
1.35 V
S3
UNCORE_V1P8_G3
V1P8A
1.8 V
G3
UNCORE_V1P8_S3
V1P8S
1.8 V
S3
UNCORE_VNN_S3
VNN
Variable
S3
See UNCORE_VNN_S3
UNCORE_VNN_SENSE
V1P24A
1.24 V
G3
USB_ULPI_V1P8_G3
V1P8A
1.8 V
G3
USB_V1P0_S3
V1P0S
1.0 V
S3
USB_V1P8_G3
V1P8A
1.8 V
G3
USB_V3P3_G3
VUSB2
3.3 V
G3
USB_HSIC_V1P24_G3
-
-
-
USB3_V1P0_G3
V1P0A
1.0 V
G3
USB3DEV_V1P0_S3
V1P0S
1.0 V
S3
VGA_V1P0_S3
V1P0S
1.0 V
S3
USB_VSSA
VSFR
1.35 V
S3
VVGA_GPIO
3.3 V
S3
VSS
-
-
-
VSSA
-
-
-
VGA_V1P35_S3_F1
VGA_V3P3_S3
Note:
USB_HSIC_V1P24_G3 pin(s) can be connected to V1P0A platform rail if USB HSIC is
not used. MIPI_V1P24_S3 can be grounded if MIPI interfaces (CSI) aren’t used.
Note:
If the VGA interface is used, LPC_V1P8V3P3_S3 must have a nominal voltage
of 3.3V.
2.29
Hardware Straps
All straps are sampled on the rising edge of PMC_CORE_PWROK. Defaults are based on
internal termination.
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Physical Interfaces
Table 31.
Straps
Signal Name
Function
Default
Strap Exit
GPIO_S0_SC[056]
Legacy
1b
PMC_CORE_PWROK
de-asserted
GPIO_S0_SC[063]
GPIO_S0_SC[065]
DDI0_DDCDATA
DDI1_DDCDATA
2.30
Legacy
Legacy
Display
Display
1b
1b
0b
0b
Strap Description
PMC_CORE_PWROK
de-asserted
PMC_CORE_PWROK
de-asserted
PMC_CORE_PWROK
de-asserted
PMC_CORE_PWROK
de-asserted
Top Swap (A16 Override)
0 = Top address bit is inverted
1 = Top address bit is unchanged
BIOS Boot Selection
0 = LPC
1 = SPI
Security Flash Descriptors
0 = Override
1 = Normal Operation
DDI0 Detect
0 = DDI0 not detected
1 = DDI0 detected
DDI1 Detect
0 = DDI1 not detected
1 = DDI1 detected
Configurable IO: GPIO Muxing
Not all interfaces may be active at the same time. To provide flexibility, some interfaces
are muxed with configurable IO balls. An interface’s signal is selected by a function
number. See Section 10.3, “Ball Name and Function by Location” on page 210 for
details of which balls are muxed, and what functions are available by ball.
Note:
2.31
Configurable IO defaults to function 0 at boot. All configurable IO with GPIO’s for
function 0 default to input at boot.
Reserved Pins
Reserved pins are non functional pins. Unless otherwise specified in this document or
related collateral, reserved pins should not be connected to anything. RSVD_GND pins
must be connect to the common ground plane (VSS), but don’t provide a return path
for currents.
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Register Access Methods
3
Register Access Methods
There are six different common register access methods:
• Fixed IO Register Access
• Fixed Memory Mapped Register Access
• IO Referenced Register Access
• Memory Referenced Register Access
• PCI Configuration Register Access (Indirect - via Memory or IO registers)
• Message Bus Register Access (Indirect - via PCI Configuration Registers)
3.1
Fixed IO Register Access
Fixed IO registers are accessed by specifying their 16-bit address in a PORT IN and/or
PORT OUT transaction from the CPU core. This allows direct manipulation of the
registers. Fixed IO registers are unmovable register in IO space.
Table 32.
Fixed IO Register Access Method Example (P80 Register)
Type: I/O Register
(Size: 32 bits)
3.2
P80: 80h
Fixed Memory Mapped Register Access
Fixed Memory Mapped IO (MMIO) registers are accessed by specifying their 32/36-bit
address in a memory transaction from the CPU core. This allows direct manipulation of
the registers. Fixed MMIO registers are unmovable registers in memory space.
Table 33.
Fixed Memory Mapped Register Access Method Example (IDX Register)
Type: Memory Mapped I/O Register
(Size: 32 bits)
3.3
IDX: FEC00000h
IO Referenced Register Access
IO referenced registers use programmable base address registers (BARs) to select a
range of IO addresses that it will use to decode PORT IN and/or PORT OUT transactions
from the CPU to directly access a register. Thus, the IO BARs act as pointers to blocks
of actual IO registers. To access an IO referenced register for a specific IO base
address, start with that base address and add the register’s offset. Example pseudo
code for an IO referenced register read is shown below:
Register_Snapshot = IOREAD([IO_BAR]+Register_Offset)
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63
Register Access Methods
Base address registers are often located in the PCI configuration space and are
programmable by the BIOS/OS. Other base address register types may include fixed
memory registers, fixed IO registers or message bus registers.
Table 34.
Referenced IO Register Access Method Example (HSTS Register)
Type: I/O Register
(Size: 8bits)
HSTS: [_IOBAR] + 0h
_IOBAR Type: PCI Configuration Register (Size: 32 bits)
_IOBAR Reference: [B:0, D:31, F:3] + 20h
3.4
Memory Referenced Register Access
The SoC uses programmable base address registers (BARs) to set a range of physical
address (memory) locations that it will use to decode memory reads and writes from
the CPU to directly access a register. These BARs act as pointers to blocks of actual
memory mapped IO (MMIO) registers. To access a memory referenced register for a
specific base address, start with that base address and add the register’s offset.
Example pseudo code for a read is shown below:
Register_Snapshot = MEMREAD([Mem_BAR]+Register_Offset)
Base address registers are often located in the PCI configuration space and are
programmable by the BIOS/OS. Other common base address register types include
fixed memory registers and IO registers that point to MMIO register blocks.
Table 35.
Memory Mapped Register Access Method Example (_MBAR Register)
Type: Memory Mapped I/O Register
(Size: 8bits)
HSTS: [_MBAR] + 0h
_MBAR Type: PCI Configuration Register (Size: 32 bits)
_MBAR Reference: [B:0, D:31, F:3] + 10h
3.5
PCI Configuration Register Access
Access to PCI configuration space registers is performed through one of two different
configuration access methods (CAMs):
• IO indexed - PCI CAM
• Memory mapped - PCI Enhanced CAM (ECAM)
Each PCI function has a standard PCI header consisting of 256 bytes for the IO access
scheme (CAM), or 4096 bytes for the enhanced memory access method (ECAM).
Invalid read accesses return binary strings of 1s.
Table 36.
PCI Register Access Method Example (VID Register)
Type: PCI Configuration Register
(Size: 16bits)
64
VID: [B:0, D:31, F:3] + 0h
Intel® Atom™ Processor E3800 Product Family
Datasheet
Register Access Methods
3.5.1
PCI Configuration Access - CAM: IO Indexed Scheme
Accesses to configuration space using the IO method relies on two 32-bit IO registers:
• CONFIG_ADDRESS - IO Port CF8h
• CONFIG_DATA - IO Port CFCh
These two registers are both 32-bit registers in IO space. Using this indirect access
mode, software uses CONFIG_ADDRESS (CF8h) as an index register, indicating which
configuration space register to access, and CONFIG_DATA (CFCh) acts as a window to
the register pointed to in CONFIG_ADDRESS. Accesses to CONFIG_ADDRESS (CF8h)
are internally captured. Upon a read or write access to CONFIG_DATA (CFCh),
configuration cycles will be generated to the PCI function specified by the address
captured in CONFIG_ADDRESS. The format of the address is shown below.
Table 37.
PCI CONFIG_ADDRESS Register (IO PORT CF8h) Mapping
Field
CONFIG_ADDRESS Bits
Enable PCI Config. Space Mapping
Note:
31
Reserved
30:24
Bus Number
23:16
Device Number
15:11
Function Number
10:08
Register/Offset Number
07:02
Bit 31 of CONFIG_ADDRESS must be set for a configuration cycle to be generated.
Pseudo code for a PCI register read is shown below:
• MyCfgAddr[23:16] = bus; MyCfgAddr[15:11] = device; MyCfgAddr[10:8] = funct;
• MyCfgAddr[7:2] = dWordMask(offset); MyCfgAddr[31] = 1;
• IOWRITE(0xCF8, MyCfgAddr)
• Register_Snapshot = IOREAD(0xCFC)
3.5.2
PCI Configuration Access - ECAM: Memory Mapped Scheme
A flat, 256 MiB memory space may also be allocated to perform configuration
transactions. This is enabled through the BUNIT.BECREG message bus register (Port:
3h, Register: 27h) found in the SoC Transaction Router. BUNIT.BECREG allows
remapping this 256 MiB region anywhere in physical memory space. Memory accesses
within the programmed MMIO range result in configuration cycles to the appropriate
PCI devices specified by the memory address as shown below.
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Register Access Methods
Table 38.
PCI Configuration Memory Bar Mapping
ECAM Memory Address Field
Note:
ECAM Memory Address Bits
Use from BAR: BUNIT.BECREG[31:28]
31:28
Bus Number
27:20
Device Number
19:15
Function Number
14:12
Register Number
11:02
ECAM accesses are only possible when BUNIT.BECREG.ECENABLE (bit 0) is set.
Pseudo code for an enhanced PCI configuration register read is shown below:
• MyCfgAddr[27:20] = bus; MyCfgAddr[19:15] = device; MyCfgAddr[14:12] =
funct;
• MyCfgAddr[11:2] = dw_offset; MyCfgAddr[31:28] = BECREG[31:28];
• Register_Snapshot = MEMREAD(MyCfgAddr)
3.6
Message Bus Register Access
Accesses to the message bus space is through the SoC Transaction Router’s PCI
configuration registers. This unit relies on three 32-bit PCI configuration registers to
generate messages:
• Message Bus Control Register (MCR) - PCI[B:0,D:0,F:0] + D0h
• Message Data Register (MDR) - PCI[B:0,D:0,F:0] + D4h
• Message Control Register eXtension (MCRX) - PCI[B:0,D:0,F:0] + D8h
This indirect access mode is similar to PCI CAM. Software uses the MCR/MCRX as an
index register, indicating which message bus space register to access (MCRX only when
required), and MDR as the data register. Writes to the MCR trigger message bus
transactions.
Writes to MCRX and MDR will be captured. Writes to MCR will generate an internal
‘message bus’ transaction with the opcode and target (port, offset, bytes) specified in
the MCR and the captured MCRX. When a write opcode is specified in MCR, the data
that was captured by MDR is used for the write. When a data read opcode is specified in
MCR, the data will be available in the MDR register after the MCR write completes (nonposted). The format of MCR and MCRX are shown below.
Table 39.
66
MCR Description (Sheet 1 of 2)
Field
MBPR Bits
OpCode (typically 10h for read, 11h for write)
31:24
Intel® Atom™ Processor E3800 Product Family
Datasheet
Register Access Methods
Table 39.
MCR Description (Sheet 2 of 2)
Field
Table 40.
MBPR Bits
Port
23:16
Offset/Register
15:08
Byte Enable
07:04
MCRX Description
MBPER
Bits
Field
Offset/Register Extension. This is used for messages sent to end points that
require more than 8 bits for the offset/register. These bits are a direct extension of
MCR[15:8].
31:08
Most message bus registers are located in the SoC Transaction Router. The default
opcode messages for those registers are as follows:
• Message ‘Read Register’ Opcode: 06h
• Message ‘Write Register’ Opcode: 07h
Registers with different opcodes will be specified as applicable. Pseudo code of a
message bus register read is shown below (where ReadOp==0x06):
• MyMCR[31:24] = ReadOp; MyMCR[23:16] = port; MyMCR[15:8] = offset;
• MyMCR[7:4] = 0xf
• PCIWRITE(0, 0, 0, 0xD0, MyMCR)
• Register_Snapshot = PCIREAD(0, 0, 0, 0xD4)
3.7
Register Field Access Types
Table 41.
Register Access Types and Definitions (Sheet 1 of 2)
Access Type
Meaning
Description
RO
Read Only
In some cases, if a register is read only, writes to this register location
have no effect. However, in other cases, two separate registers are located
at the same location where a read accesses one of the registers and a write
accesses the other register. See the I/O and memory map tables for
details.
WO
Write Only
In some cases, if a register is write only, reads to this register location
have no effect. However, in other cases, two separate registers are located
at the same location where a read accesses one of the registers and a write
accesses the other register. See the I/O and memory map tables for
details.
R/W
Read/Write
A register with this attribute can be read and written.
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67
Register Access Methods
Table 41.
Register Access Types and Definitions (Sheet 2 of 2)
Access Type
Meaning
Description
R/WC
Read/Write Clear
A register bit with this attribute can be read and written. However, a write
of 1 clears (sets to 0) the corresponding bit and a write of 0 has no effect.
R/WO
Read/Write-Once
A register bit with this attribute can be written only once after power up.
After the first write, the bit becomes read only.
R/WLO
Read/Write, LockOnce
A register bit with this attribute can be written to the non-locked value
multiple times, but to the locked value only once. After the locked value
has been written, the bit becomes read only.
Default
Default
When the processor is reset, it sets its registers to predetermined default
states. The default state represents the minimum functionality feature set
required to successfully bring up the system. Hence, it does not represent
the optimal system configuration. It is the responsibility of the system
initialization software to determine configuration, operating parameters,
and optional system features that are applicable, and to program the
processor registers accordingly.
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Mapping Address Spaces
4
Mapping Address Spaces
The SoC supports four different address spaces:
• Physical Address Space Mappings
• IO Address Space
• PCI Configuration Space
• Message Bus Space
The CPU core can only directly access memory space through memory reads and writes
and IO space through the IN and OUT IO port instructions. PCI configuration space is
indirectly accessed through IO or memory space, and the Message Bus space is
accessed through PCI configuration space. See Chapter 3, “Register Access Methods”
for details.
This chapter describes how the memory, IO, PCI and Message Bus spaces are mapped
to interfaces in the SoC.
Note:
4.1
See Chapter 13, “SoC Transaction Router” for registers specified in the chapter.
Physical Address Space Mappings
There are 64 GB (36-bits) of physical address space that can be used as:
• Memory Mapped IO (MMIO - IO fabric)
• Physical Memory (DRAM)
The CPU core can access the full physical address space, while downstream devices can
only access SoC DRAM, and each CPU core’s local APIC. Peer to peer transactions are
not supported.
Most devices map their registers and memory to the physical address space. This
chapter summarizes the possible mappings.
4.1.1
SoC Transaction Router Memory Map
The SoC Transaction Router maps the physical address space as follows:
• CPU core to DRAM
• CPU core to IO fabric (MMIO)
• CPU core to extended PCI registers (ECAM accesses)
• IO fabric to CPU cores (local APIC interrupts)
Although 64 GB (36-bits) of physical address space is accessible, some MMIO must
exist for devices and software with 32-bit limits. Further, all DRAM should remain
accessible for devices and software with access to memory above 4 GB. These goals
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69
Mapping Address Spaces
are accomplished by moving a section DRAM to start at the fixed 4 GB boundary,
leaving a hole below 4 GB for MMIO. This creates the following distinct memory
regions:
• DOS DRAM + Low DRAM
• Low MMIO
• High DRAM
• High MMIO
There are two registers used to create these regions, BMBOUND and BMBOUND_HI.
Their use is shown in Figure 4.
Figure 4.
Physical Address Space - DRAM & MMIO
64 GB
High MMIO
BMBOUND_HI
High DRAM
4 GB
Low MMIO
High DRAM
BMBOUND
Low DRAM
Low DRAM
DOS DRAM
DOS DRAM
Physical Address
Space
DRAM Address
Space
1 MB
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Mapping Address Spaces
4.1.1.1
Low MMIO
The low MMIO mappings are shown in Figure 5.
Figure 5.
Physical Address Space - Low MMIO
64 GB
Boot Vector
High MMIO
- 1 (FFFFFFFFh)
- 64 KB (FFFF0000h)
- 17 MB (FEF00000h)
Local APIC
High DRAM
- 18 MB (FEE00000h)
4 GB
- 20 MB (FEBFFFFFh)
Low MMIO
Abort Page
- 21 MB (FEB00000h)
BMBOUND
BEGREG + 256 MB
Low DRAM
PCI ECAM
BECREG
1 MB
DOS DRAM
Physical Address
Space
By default, CPU core reads targeting the Boot Vector range (FFFFFFFFh-FFFF0000h)
are sent to the boot Flash connected to the Platform Controller Unit, and write accesses
target DRAM. This allows the boot strap CPU core to fetch boot code from the boot
Flash, and then shadow that code to DRAM.
Upstream writes from the IO fabric to the Local APIC range (FEE00000h-FEF00000h)
are sent to the appropriate CPU core’s APIC.
Write accesses from a CPU core to the Abort Page range (FEB00000h-FEBFFFFFh) will
be dropped, and reads will always return all 1’s in binary.
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Mapping Address Spaces
Accesses in the 256 MB PCI ECAM range starting at BECREG generate enhanced PCI
configuration register accesses when enabled (BECREG.ECENABLE). Unlike traditional
memory writes, writes to this range are non-posted when enabled. See Chapter 3,
“Register Access Methods” for more details.
All other downstream accesses in the Low MMIO range are sent to the IO Fabric for
further decode based on PCI resource allocations. The IO Fabric’s subtractive agent (for
unclaimed accesses) is the Platform Controller Hub.
4.1.1.2
DOS DRAM
The DOS DRAM is the memory space below 1 MB. In general, accesses from a
processor targeting DOS DRAM target system DRAM. Exceptions are shown in the
below figure.
Figure 6.
Physical Address Space - DOS DRAM
64 GB
High MMIO
High DRAM
4 GB
Low MMIO
BMBOUND
PROM ‘F’ Segment
64 KB (F0000h to FFFFFh)
PROM ‘E’ Segment
64 KB (E0000h to EFFFFh)
Low DRAM
VGA/CSEG
128 KB (A0000h to BFFFFh)
1 MB
DOS DRAM
Physical Address
Space
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Mapping Address Spaces
Processor writes to the 64 KB (each) PROM ‘E’ and ‘F’ segments (E0000h-EFFFFh and
F0000h-FFFFFh) always target DRAM. The BMISC register is used to direct CPU core
reads in these two segments to DRAM or the IO fabric (MMIO).
CPU core accesses to the 128 KB VGA/CSEG range (A0000h-BFFFFh) can target DRAM
or the IO fabric (MMIO). The target is selected with the BMISC.ABSEGINDRAM register.
4.1.1.3
Additional Mappings
There are two additional mappings available in the SoC Transaction Router:
• SMM range
• Non-snoop range
Figure 7 shows these mappings.
Figure 7.
Physical Address Space - SMM and Non-Snoop Mappings
Low or High DRAM in
Physical Space
Physical Address
Space
BSMMRRH (SMM Range Hi)
SMM Range
BSMMRRL (SMM Range Lo)
Non-Snoopable
Memory
64 GB
BNOCACHE.Upper...
BNOCACHE.Lower...
0
SMI handlers running on a CPU core execute out of SMM memory. To protect this
memory from non-CPU core access, the SMM Range (BSMMRRL-BSMMRRH) may be
programmed anywhere in low or high DRAM space (1 MB aligned). This range will only
allow accesses from the CPU cores.
To prevent snoops of the CPU cores when DMA devices access a specific memory
region, the Non-Snoopable Memory range (BNOCACHE.Lower-BNOCACHE.Upper)
can be programmed anywhere in physical address space. This range is enabled via the
BNOCACHECTL register’s enable bit (BNOCACHECTL.Enable).
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Mapping Address Spaces
4.1.2
IO Fabric (MMIO) Map
Memory accesses targeting MMIO are routed by the IO fabric to programmed PCI
ranges, or routed to the PCU by default (subtractive agent). Programmed PCI ranges
can be moved within low or high MMIO, and most can be disabled.
Note:
Not all devices can be mapped to high MMIO.
Fixed MMIO is claimed by the Platform Controller Unit (PCU). The default regions are
listed below. Movable ranges are not shown. See the register maps of all PCU devices
for details.
Table 42.
Fixed Memory Ranges in the Platform Controller Unit (PCU)
Start
Address
End
Address
Low BIOS (Flash Boot)
000E0000h
000FFFFFh
Starts 128 KB below 1 MB; Firmware/
BIOS
IO APIC
FEC00000h
FEC00040h
Starts 20 MB below 4 GB
HPET
FED40000h
FED40FFFh
Starts 19 MB below 4 GB
TPM (LPC)
FFD40000h
FFD40FFFh
Starts 16 KB above HPET range
High BIOS/Boot Vector
FFFF0000h
FFFFFFFFh
Starts 64 KB below 4 GB; Firmware/
BIOS
Device
Comments
The following PCI devices may claim memory resources in MMIO space:
• Graphics/Display (High MMIO capable)
• PCI Express* (High MMIO capable)
• SATA
• SD/MMC/SDIO
• SIO
• HD Audio
• Platform Controller Unit (PCU) (Multiple BARs)
• xHCI USB
• EHCI USB
• USB Device
• LPE/I2S
• ISP/MIPI-CSI
See each device’s interface chapter for details.
Warning:
74
Variable memory ranges should not be set to conflict with other memory ranges. There
will be unpredictable results if the configuration software allows conflicts to occur.
Hardware does not check for conflicts.
Intel® Atom™ Processor E3800 Product Family
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Mapping Address Spaces
4.2
IO Address Space
There are 64 KB + 3 bytes of IO space (0h-10002h) for accessing IO registers. Most IO
registers exists for legacy functions in the PCU or for PCI devices, while some are
claimed by the SoC Transaction Router for graphics and for the PCI configuration space
access registers.
4.2.1
SoC Transaction Router IO Map
The SoC claims IO transactions for VGA/Extended VGA found in the display/graphics
interface. It also claims the two 32-bit registers at port CF8h and CFCh used to access
PCI configuration space.
4.2.2
IO Fabric IO Map
4.2.2.1
PCU Fixed IO Address Ranges
Below table shows the fixed IO space ranges seen by a processor.
Table 43.
Fixed IO Ranges in the Platform Controller Unit (PCU)
Device
4.2.2.2
IO Address
8259 Master
20h-21h, 24h-25h,
28h-29h, 2Ch-2Dh,
30h-31h, 34h-35h,
38h-39-, 3Ch-3Dh
8254s
40h-43h, 50h-53h
PS2 Control
60h, 64h
NMI Controller
61h, 63h, 65h, 67h
RTC
70h-77h
Port 80h
80h-83h
Init Register
92h
8259 Slave
A0h-A1h, A4h-A5h, A8hA9h, ACh-ADh, B0h-B1h,
B4h-B5h, B8h-B9h, BChBDh, 4D0h-4D1h
PCU UART
3F8h-3FFh
Reset Control
CF9h
Active Power Management
B2h-B3h
Comments
Overlaps PCI IO registers
Variable IO Address Ranges
Table 44 shows the variable IO decode ranges. They are set using base address
registers (BARs) or other similar means. Plug-and-play (PnP) software (PCI/ACPI) can
use their configuration mechanisms to set and adjust these values.
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Mapping Address Spaces
Warning:
The variable IO ranges should not be set to conflict with other IO ranges. There will be
unpredictable results if the configuration software allows conflicts to occur. Hardware
does not check for conflicts.
Table 44.
Movable IO Ranges Decoded by PCI Devices on the IO Fabric
Size
(bytes)
Device
4.3
Target
ACPI Power Management
(PCU)
128
ACPI_BASE_ADDR (PM1BLK): PCI[B:0,D:31,F:0] +
40h
SMBus (PCU)
32
SMBA: PCI[B:0,D:31,F:3] + 20h
GPIO (PCU)
256
GBA: PCI[B:0,D:31,F:0] + 48h
RCBA (PCU)
1024
RCRB_BA: PCI[B:0,D:31,F:0] + F0h
PCI Configuration Space
All PCI devices/functions are shown below. Table below will always take priority.
Table 45.
PCI Devices and Functions (Sheet 1 of 2)
Bus
Device
Function
Device ID
0
0
0
0F00h
SoC Transaction Router
0
2
0
0F31h
Graphics & Display
0
3
0
0F38h
Camera Image Signal
Processor
0
16
0
0F14h
Storage Control Cluster
(SCC)
0
17
0
0F15h
SDIO Port
0
18
0
0F16h
SD Port
0
19
0
0F20h (IDE)
0F21h (IDE)
0F22h (AHCI)
0F23h (AHCI)
0
20
0
0F35h
xHCI USB
0
21
0
0F28h
Low Power Engine Audio
0
22
0
0F37h
USB Device
0
23
0
0F50h
Storage Control Cluster
(SCC)
76
Device Description
Function Description
eMMC Port (de-featured - use Device
23 instead)
SATA
Host Bridge + three I2S Ports (0-2)
eMMC 4.5 Port
Intel® Atom™ Processor E3800 Product Family
Datasheet
Mapping Address Spaces
Table 45.
PCI Devices and Functions (Sheet 2 of 2)
Bus
Device
Function
Device ID
Device Description
0
24
0
0F40h
1
0F41h
I2C Port 1
2
0F42h
I2C Port 2
3
0F43h
I2C Port 3
4
0F44h
I2C Port 4
5
0F45h
I2C Port 5
6
0F46h
I2C Port 6
7
0F47h
I2C Port 7
0F18h
Serial IO (SIO)
Function Description
DMA
0
26
0
Trusted Execution Engine
0
27
0
0F04h
HD Audio
0
28
0
0F48h
PCI Express*
1
0F4Ah
Root Port 2
2
0F4Ch
Root Port 3
Root Port 1
3
0F4Eh
0
29
0
0F34h
EHCI USB
Root Port 4
0
30
0
0F06h
Serial IO (SIO)
1
0F08h
PWM Port 1
2
0F09h
PWM Port 2
3
0F0Ah
HSUART Port 1
4
0F0Ch
HSUART Port 2
5
0F0Eh
SPI Port
DMA
0
31
0
0F1Ch
Platform Controller Unit
LPC: Bridge to Intel Legacy Block
0
31
3
0F12h
Platform Controller Unit
SMBus Port
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Mapping Address Spaces
Figure 8.
Bus 0 PCI Devices and Functions
CPU
Core
SoC Transaction
Router
D:0,F:0
PCI
CAM
(I/O)
PCI
ECAM
(Mem)
Graphics
D:2,F:0
Bus 0
Camera ISP
D:3,F:0
SD/
MMC
xHCI USB
D:20,F:0
USB Dev
D:22,F:0
I2C4 F:5
I2C5 F:6
#3 D:18,F:0
LPE Audio (I2S)
D:21,F:0
SIO D:24
I2C2 F:3
I2C3 F:4
#2 D:17,F:0
SATA
D:19,F:0
DMA F:0
I2C0 F:1
I2C1 F:2
#1 D:16,F:0
I2C6 F:7
RP2 F:1
RP3 F:2
RP4 F:3
PCIe D:28
RP1 F:0
TXE
D:26,F:0
HDA
D:27,F:0
SMB F:3
PCU
D:31
LPC (iLB) F:0
SIO D:30
EHCI USB
D:29,F:0
DMA F:0
PWM1 F:1
PWM2 F:2
HSUART1 F:3
HSUART2 F:4
SPI F:5
§
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Datasheet
Integrated Clock
5
Integrated Clock
Clocks are integrated, consisting of multiple variable frequency clock domains, across
different voltage domains. This architecture achieves a low power clocking solution that
supports the various clocking requirements of the SoC’s many interfaces.
Integrated Clock
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O
79
Integrated Clock
Figure 9.
Clocking Example
HDMI/eDP/DP
Misc
DDI[1:0]_TXP/N[3]
DDI[1:0]_DDCCLK
DRAM0_CLKP/N[2,0]
DRAM CHANNEL 0
DRAM1_CLKP/N[2,0]
DRAM CHANNEL 1
MMC1_CLK
eMMC
SDIO2_CLK
SDIO
SD3_CLK
SD CARD
PMC_PLT_CLK[5:0]
25MHz
Primary Reference
iClock
32kHz
Primary Reference
Clock Inputs
And Outputs
PMC_SUSCLK[3:0]
PCIe
5.1
PCIE_CLKP/N[3:0]
SIO_I2C5_CLK
SVID_CLK
Power
Management/Seq.
Features
Platform clocking is provided internally by the Integrated Clock logic. No external clock
chips are required for the SoC to function. All the required platform clocks are provided
by two crystal inputs: a 25 MHz primary reference for the integrated clock block and a
32.768 kHz reference for the Real Time Clock (RTC) block.
The different inputs and outputs are listed below.
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Integrated Clock
Table 46.
SoC Clock Inputs
Clock Domain
Table 47.
Signal Name
Frequency
Usage/Description
Main
ICLK_OSCIN
ICLK_OSCOUT
25 MHz
Reference crystal for the iCLK PLL
RTC
ILB_RTC_X1
ILB_RTC_X2
32.768 kHz
RTC crystal I/O for RTC block
MIPI CSI
MCSI1_CLKP/N
MCSI2_CLKP/N
MCSI3_CLKP/N
80-500 MHz
Clocks for cameras
LPC
ILB_LPC_CLK[1]
33 MHz
Can be configured as an input to
compensate for board routing delays
through Soft Strap.
USB PHY
USB_ULPI_CLK
60 MHz
Interface clock from ULPI PHY.
SoC Clock Outputs (Sheet 1 of 2)
Clock Domain
Signal Name
Frequency
Usage/Description
Memory
DRAM0_CKP/N[2,0]
DRAM1_CKP/N[2,0]
533/667 MHz
Drives the Memory ranks 0-1. Data
rate (MT/s) is 2x the clock rate.
Note: The frequency is fused in each
SoC. It is not possible to support both
frequencies on one SoC.
eMMC
MMC1_CLK
MMC1_45_CLK
25-50 MHz
25-200 MHz
Clock for eMMC 4.41 devices
Clock for eMMC 4.51 devices
Actual clock can run as low as 400
kHz during initialization.
SDIO
SD2_CLK
25-50 MHz
Clock for SDIO devices
SD Card
SD3_CLK
25-50 MHz
Clock for SD card devices
SPI
PCU_SPI_CLK
20 MHz,
33 MHz,
50 MHz
Clock for SPI flash
PMIC/COMMS
PMC_SUSCLK[3:0]
32.768 kHz
Pass through clock from RTC oscillator
LPC
ILB_LPC_CLK[0:1]
33 MHz
Provided to devices requiring LPC
clock
HDA
HDA_CLK
24 MHz
Serial clock for external HDA codec
device
PCI Express
PCIE_CLKN[3:0]
PCIE_CLKP[3:0]
100 MHz
Differential Clocks supplied to
external PCI express devices based
on assertion of PCIE_CLKREQ[3:0]#
inputs
USB PHY
USB_ULPI_REFCLK
19.2 MHz
Clock for USB devices
HDMI
DDI[1:0]_TXP/N[3]
25-148.5 MHz
Differential clock for HDMI devices
HDMI DDC
DDI[1:0]_DDCCLK
100 kHz
Clock for HDMI DDC devices
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Datasheet
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Integrated Clock
Table 47.
SoC Clock Outputs (Sheet 2 of 2)
Clock Domain
VGA DDC
Signal Name
VGA_DDCCLK
Frequency
Usage/Description
100 kHz
Clock for VGA DDC devices
SVID
SVID_CLK
25 MHz
Clock used by voltage regulator
I2S
LPE_I2S[2:0]_CLK
12.5 MHz
Continuous serial clock for I2S
interfaces
Platform Clocks
PMC_PLT_CLK [5:0]
25 MHz
Platform
PLT_CLK
PLT_CLK
PLT_CLK
PLT_CLK
SIO SPI
SIO_SPI_CLK
15 MHz
SPI clock output
I C
SIO_I2C[6:0]_CLK
100 kHz,
400 kHz,
1 MHz,
3.4 MHz
I2C clocks
Note: In I2C Controller the parameter
called IC_CAP_LOADING can be set to
400pf/100pf. As per specification
3.4MHz is supported in 100pf loading
while 1.7MHz is the max frequency at
400pf load.
SMBus
PCU_SMB_CLK
10 kHz 100 kHz
Drives SMBus device
2
clocks. For example:
[2:0] - Camera
[3] - Audio Codec
[4] [5] - COMMs
§
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Datasheet
Power Management
6
Power Management
This chapter provides information on the following power management topics:
• ACPI States
• Processor Core
• PCI Express
• Integrated Graphics Controller
6.1
Power Management Features
• ACPI System States support (S0, S3, S4, S5)
• Processor Core/Package States support (C0 – C6)
• SoC Graphics Adapter States support D0 – D3.
• Support Link Power Management (LPM)
• Thermal throttling
• Dynamic I/O power reductions (disabling sense amps on input buffers, tri-stating
output buffers)
• Active power down of Display links
6.2
Power Management States Supported
The Power Management states supported by the processor are described in this
section.
6.2.1
S-State Definition
6.2.1.1
S0 - Full On
This is the normal operating state of the processor. In S0, the core processor will
transition in and out of the various processor C-States and P-States.
6.2.1.2
S3 - Suspend to RAM (Standby)
S3 is a suspend state in which the core power planes of the processor are turned off
and the suspend wells remain powered.
• All power wells are disabled, except for the suspend and RTC wells.
• The core processor’s macro-state is saved in memory.
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Power Management
• Memory is held in self-refresh and the memory interface is disabled, except the
CKE pin as it is powered from the memory voltage rail. CKE is driven low.
6.2.1.3
S4 - Suspend to Disk (Hibernate)
S4 is a suspend state in which most power planes of the processor are turned off,
except for the suspend and RTC well. In this ACPI state, system context is saved to the
hard disk.
Key features:
• No activity is allowed.
• All power wells are disabled, except for the suspend and RTC well.
6.2.1.4
S5 - Soft Off
From a hardware perspective the S5 state is identical to the S4 state. The difference is
purely software; software does not write system context to hard disk when entering
S5.
The following table shows the differences in the sleeping states with regards to the
processor’s output signals.
NOTES:
Table 48.
SoC Sx-States to SLP_S*#
State
S0
S3
S4
S5
Reset w/o
Power Cycle
Reset w/
Power Cycle
CPU Executing
In C0
OFF
OFF
OFF
No
OFF
PMC_SLP_S3#
HIGH
LOW
LOW
LOW
HIGH
LOW
PMC_SLP_S4#
HIGH
HIGH
LOW
LOW
HIGH
LOW
S0 Power Rails
ON
OFF
OFF
OFF
ON
OFF
PMC_PLTRST#
HIGH
LOW
LOW
LOW
LOW
LOW
PMC_SUS_STAT#
HIGH
LOW
LOW
LOW
HIGH
LOW
PCIe Links
L0, L1
L3
L3
L3
L3 Ready
L3
NOTES:The processor treats S4 and S5 requests the same. The processor does not have
PMC_SLP_S5#. PMC_SUS_STAT# is required to drive low (asserted) even if core well is left
on because PMC_SUS_STAT# also warns of upcoming reset.
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Power Management
6.2.2
Table 49.
System States
General Power States for System
States/Substates
Legacy Name / Description
G0/S0/C0
FULL ON: CPU operating. Individual devices may be shut down to save
power. The different CPU operating levels are defined by Cx states.
G0/S0/Cx
Cx State: CPU manages C-state itself.
G1/S3
Suspend-To-RAM(STR): The system context is maintained in system
DRAM, but power is shut to non-critical circuits. Memory is retained, and
refreshes continue. All external clocks are shut off; RTC clock and internal
ring oscillator clocks are still toggling.
G1/S4
Suspend-To-Disk (STD): The context of the system is maintained on the
disk. All of the power is shut down except power for the logic to resume.
The S4 and S5 states are treated the same.
G2/S5
Soft-Off: System context is not maintained. All of the power is shut down
except power for the logic to restart. A full boot is required to restart. A full
boot is required when waking.
The S4 and S5 states are treated the same.
SoC G3
SoC Mechanical OFF. System context is not maintained. All power to the
SoC is shutdown except for the RTC. All of the power to the rest of the
system is shut down except power for the logic to restart. No SoC “Wake”
events are possible, because the SoC does not have any power. when SoC
power returns, transition will depend on the state just prior to the entry to
SoC G3.
G3
Mechanical OFF. System is not maintained. All power shutdown except for
the RTC. No “Wake” events are possible, because the system does not have
any power. This state occurs if the user removes the batteries, turns off a
mechanical switch, or if the system power supply is at a level that is
insufficient to power the “waking” logic. When system power returns,
transition will depend on the state just prior to the entry to G3.
Table 50 shows the transitions rules among the various states. Note that transitions
among the various states may appear to temporarily transition through intermediate
states. These intermediate transitions and states are not listed in the table.
Table 50.
ACPI PM State Transition Rules (Sheet 1 of 2)
Present
State
G0/S0/C0
Transition Trigger
Next State
IA Code MWAIT or LVL Rd
C0/S0/Cx
PM1_CNT.SLP_EN bit set
G1/Sx or G2/S5 state (specified by
PM1_CNT.SLP_TYP)
Power Button Override
G2/S5
Mechanical Off/Power Failure
G3
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Power Management
Table 50.
ACPI PM State Transition Rules (Sheet 2 of 2)
Present
State
Transition Trigger
G0/S0/Cx
Cx break events which include: CPU
snoop, MSI, Legacy Interrupt, AONT
timer
G0/S0/C0
Power Button Override
G2/S5
System Power Failure
G3
Any Enabled Wake Event
G0/S0/C0
Power button Override
G2/S5
Resume Well Power Failure
G3
G2/S5
Any Enabled Wake Event
G0/S0/C0
Resume Well Power Failure
G3
G3
Power Returns
Option to go to S0/C0 (reboot) or G2/S5
(stay off until power button pressed or
other enabled wake event) or G1/S4 (if
system state was S4 prior to the power
failure). Some wake events are
preserved through a power failure.
G1/S3,G1/S4
6.2.3
Table 51.
Next State
Processor States
Processor Core/ States Support
State
6.2.4
Table 52.
Description
C0
Active mode, processor executing code
C1
AutoHALT state
C6
Deep Power Down. Prior to entering the Deep Power Down
Technology (code named C6) State, The core process will flush its
cache and save its core context to a special on die SRAM on a
different power plane. Once Deep Power Down Technology (code
named C6) sequence has completed. The core processor’s voltage
is completely shut off.
Integrated Graphics Display States
SoC Graphics Adapter State Control
State
86
Description
D0
Full on, Display active
D3
Power off display
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Power Management
6.2.5
Table 53.
Integrated Memory Controller States
Main Memory States
States
6.2.6
Table 54.
Description
Powerup
CKE asserted. Active mode.
Precharge Powerdown
CKE de-asserted (not self-refresh) with all banks closed.
Active Powerdown
CKE de-asserted (not self-refresh) with at least one bank active.
Self-Refresh
CKE de-asserted using device self-refresh
PCI Express* (PCIe*) States
PCI Express* States
States
6.2.7
Table 55.
Description
L0
Full on – Active transfer state
L0s
First Active Power Management low power state – Low exit latency
L1
Lowest Active Power Management - Longer exit latency
L3
Lowest power state (power-off) – Longest exit latency
Interface State Combinations
G, S and C State Combinations
Global
(G) State
Sleep
(S) State
Processor
Core
(C) State
Processor
State
System Clocks
Description
G0
S0
C0
Full On
On
Full On
G0
S0
C1
Auto-Halt
On
Auto-Halt
G0
S0
C6
Deep Power
Down
On
Deep Power Down
G1
S3
Power off
Off except RTC & internal
ring OSC
Suspend to RAM
G1
S4
Power off
Off except RTC & internal
ring OSC
Suspend to Disk
G2
S5
Power off
Off except RTC & internal
ring OSC
Soft Off
G3
NA
Power Off
Power off
Hard Off
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Power Management
Table 56.
D, S and C State Combinations
Graphics Adapter
(D) State
Sleep (S) State
(C) State
D0
S0
C0
Full On, Displaying
D0
S0
C1
Auto-Halt, Displaying
D0
S0
C6
Deep Sleep, Display Off
D3
S0
Any
Not Displaying
D3
S3
Not Displaying
Graphics Core power off.
D3
S4
Not Displaying
Suspend to disk
Core power off
Description
NOTE:S0ix is not supported for Bay Trail-M/D and Bay Trail-I.
6.3
Processor Core Power Management
While executing code, Enhanced Intel® SpeedStep® Technology optimizes the
processor’s frequency and core voltage based on workload. Each frequency and voltage
operating point is defined by ACPI as a P-state. When the processor is not executing
code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, lower
power C-states have longer entry and exit latencies.
6.3.1
Enhanced Intel® SpeedStep® Technology
The following are the key features of Enhanced Intel® SpeedStep® Technology:
• Applicable to Processor Core Voltage and Graphic Core Voltage
• Multiple frequency and voltage points for optimal performance and power
efficiency. These operating points are known as P-states.
• Frequency selection is software controlled by writing to processor MSRs. The
voltage is optimized based on the selected frequency:
— If the target frequency is higher than the current frequency, Core_VCC_S3 is
ramped up slowly to an optimized voltage. This voltage is signaled by the SVID
signals to the voltage regulator. Once the voltage is established, the PLL locks
on to the target frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the
target frequency, then transitions to a lower voltage by signaling the target
voltage on the SVID signals.
• The processor controls voltage ramp rates by requesting appropriate ramp rates
from an external SVID controller.
• Because there is low transition latency between P-states, a significant number of
transitions per second are possible.
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• Thermal Monitor mode.
— Refer to Chapter 8, “Thermal Management”
6.3.2
Dynamic Cache Sizing
Dynamic Cache Sizing allows the processor to flush and disable a programmable
number of L2 cache ways upon each Deeper Sleep entry under the following condition:
• The C0 timer that tracks continuous residency in the Normal state, has not expired.
This timer is cleared during the first entry into Deeper Sleep to allow consecutive
Deeper Sleep entries to shrink the L2 cache as needed.
• The predefined L2 shrink threshold is triggered.
The number of L2 cache ways disabled upon each Deeper Sleep entry is configured in
the BBL_CR_CTL3 MSR. The C0 timer is referenced through the
CLOCK_CORE_CST_CONTROL_STT MSR. The shrink threshold under which the L2
cache size is reduced is configured in the PMG_CST_CONFIG_CONTROL MSR. If the
ratio is zero, then the ratio will not be taken into account for Dynamic Cache Sizing
decisions. Refer to the BIOS Writer’s Guide for more details.
6.3.3
Low-Power Idle States
When the processor core is idle, low-power idle states (C-states) are used to save
power. More power savings actions are taken for numerically higher C-state. However,
higher C-states have longer exit and entry latencies. Resolution of C-state occur at the
thread, processor core, and processor core level.
6.3.3.1
Clock Control and Low-Power States
The processor core supports low power states at core level. The central power
management logic ensures the entire processor core enters the new common processor
core power state. For processor core power states higher than C1, this would be done
by initiating a P_LVLx (P_LVL6) I/O read to all of the cores. States that require external
intervention and typically map back to processor core power states. States for
processor core include Normal (C0, C1).
The processor core implements two software interfaces for requesting low power
states: MWAIT instruction extensions with sub-state specifies and P_LVLx reads to the
ACPI P_BLK register block mapped in the processor core’s I/O address space. The
P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the
processor core and do not directly result in I/O reads on the processor core bus. The
monitor address does not need to be setup before using the P_LVLx I/O read interface.
The sub-state specifications used for each P_LVLx read can be configured in a software
programmable MSR by BIOS.
The Cx state ends due to a break event. Based on the break event, the processor
returns the system to C0. The following are examples of such break events:
• Any unmasked interrupt goes active
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• Any internal event that will cause an NMI or SMI_B
• CPU Pending Break Event (PBE_B)
• MSI
Figure 10. Idle Power Management Breakdown of the Processor Cores
Core 0 State
Core 1 State
Processor Package State
6.3.4
Processor Core C-States Description
The following state descriptions assume that both threads are in common low power
state.
6.3.4.1
Core C0 State
The normal operating state of a core where code is being executed.
6.3.4.2
Core C1 State
C1 is a low power state entered when a core execute a HLT or MWAIT(C1) instruction.
A System Management Interrupt (SMI) handler returns execution to either Normal
state or the C1 state. See the Intel® 64 and IA-32 Architecture Software Developer’s
Manual, Volume 3A/3B: System Programmer’s Guide for more information.
While a core is in C1 state, it processes bus snoops and snoops from other threads.
6.3.4.3
Core C6 State
Individual core can enter the C6 state by initiating a P_LVL3 I/O read or an MWAIT(C6)
instruction. Before entering core C6, the core will save its architectural state to a
dedicated SRAM. Once complete, a core will have its voltage reduced to zero volts.
During exit, the core is powered on and its architectural state is restored.
There are various types of C-state:
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• C6NS implies only the core should be powergated, but the L2 cache contents
should be retained.
6.3.5
Package C-States
The processor supports C0, C1, and C6 power states. The following is a summary of the
general rules for package C-state entry. These apply to all package C-states unless
specified otherwise:
• Package C-state request is determined by the lowest numerical core C-state
amongst all cores.
• A package C-state is automatically resolved by the processor depending on the
core idle power states and the status of the platform components.
• Each core can be at a lower idle power state than the package if the platform does
not grant the processor permission to enter a requested package C-state.
• The platform may allow additional power savings to be realized in the processor.
• For package C-states, the processor is not required to enter C0 before entering any
other C-state.
• Entry in to a package C-state may be subject to auto-demotion - that is the
processor may keep the package in a shallower package C-state then requested by
the OS if the processor determines via heuristics that the shallower C-state results
in better power/performance.
The processor exits a package C-state when a break event is detected. Depending on
the type of break event, the processor does the following:
• If a core break event is received, the target core is activated and the break event
message is forwarded to the target core.
— If the break event is not masked, the target core enters the core C0 state and
the processor enters package C0.
— If the break event is masked, the processor attempts to re-enter its previous
package state.
• If the break event was due to a memory access or snoop request.
— But the platform did not request to keep the processor in a higher package Cstate, the package returns to its previous C-state.
— And the platform requests a higher power C-state, the memory access or snoop
request is serviced and the package remains in the higher power C-state.
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Core/Module 0
Package C-State
Core/Module 1
C0
C1
C6NS
C0
C0
C0
C0
C1
C0
C1
C1
C0
C1
C6NS
C6NS
NOTE:
1.
2 Cores of the SoC will make up one module.
Figure 11. Package C-state Entry and Exit
C0
C1
6.3.5.1
C6
Package C0
The normal operating state for the processor. The processor remains in the normal
state when at least one of its cores is in the C0 state or when the platform has not
granted permission to the processor to go into a low power state. Individual cores may
be in lower power idle states while the package is in C0.
6.3.5.2
Package C1
No additional power reduction actions are taken in the package C1 state.
The package enters the C1 low power state when:
• At least one core is in the C1 state.
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• The other cores are in a C1 or lower power state.
No notification to the system occurs upon entry to C1.
6.3.5.3
Package C6 State
A processor enters the package C6 low power state when:
• At least one core is in the C6 state.
• The other cores are in a C6 or lower power state, and the processor has been
granted permission by the platform.
• The platform has allowed a package C6 state.
In package C6 state, all cores have saved their architectural state and have had their
core voltages reduced to zero volts.
6.3.6
Graphics Power Management
6.3.6.1
Graphics and video decoder C-State
GFX C-State (GC6) and VED C-state (VC6) are designed to optimize the average power
to the graphics and video decoder engines during times of idleness. GFX C-state is
entered when the graphics engine, has no workload being currently worked on and no
outstanding graphics memory transactions. VED S-state is entered when the video
decoder engine has no workload being currently worked on and no outstanding video
memory transactions. When the idleness condition is met, the processor will power
gate the Graphics and video decoder engines.
6.3.6.2
Intel® Display Power Saving Technology (Intel® DPST)
The Intel DPST technique achieves backlight power savings while maintaining visual
experience. This is accomplished by adaptively enhancing the displayed image while
decreasing the backlight brightness simultaneously. The goal of this technique is to
provide equivalent end-user image quality at a decreased backlight power level.
1. The original (input) image produced by the operating system or application is
analyzed by the Intel DPST subsystem. An interrupt to Intel® DPST software is
generated whenever a meaningful change in the image attributes is detected. (A
meaningful change is when the Intel DPST software algorithm determines that
enough brightness, contrast, or color change has occurred to the displaying images
that the image enhancement and backlight control needs to be altered.)
2. Intel DPST subsystem applies an image-specific enhancement to increase image
contrast, brightness, and other attributes.
3. A corresponding decrease to the backlight brightness is applied simultaneously to
produce an image with similar user-perceived quality (such as brightness) as the
original image. Intel DPST 5.0 has improved the software algorithms and has minor
hardware changes to better handle backlight phase-in and ensures the documented
and validated method to interrupt hardware phase-in.
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6.3.6.3
Intel® Automatic Display Brightness
The Intel Automatic Display Brightness feature dynamically adjusts the backlight
brightness based upon the current ambient light environment. This feature requires an
additional sensor to be on the panel front. The sensor receives the changing ambient
light conditions and sends the interrupts to the Intel Graphics driver. As per the change
in Lux, (current ambient light illuminance), the new backlight setting can be adjusted
through BLC. The converse applies for a brightly lit environment. Intel Automatic
Display Brightness increases the back light setting.
6.3.6.4
Intel® Seamless Display Refresh Rate Switching Technology (Intel®
SDRRS Technology)
When a Local Flat Panel (LFP) supports multiple refresh rates, the Intel® Display
Refresh Rate Switching power conservation feature can be enabled. The higher refresh
rate will be used when on plugged in power or when the end user has not selected/
enabled this feature. The graphics software will automatically switch to a lower refresh
rate for maximum battery life when the design application is on battery power and
when the user has selected/enabled this feature.
There are two distinct implementations of Intel SDRRS—static and seamless. The static
Intel SDRRS method uses a mode change to assign the new refresh rate. The seamless
Intel SDRRS method is able to accomplish the refresh rate assignment without a mode
change and therefore does not experience some of the visual artifacts associated with
the mode change (SetMode) method.
6.4
Memory Controller Power Management
The main memory is power managed during normal operation and in low-power ACPI
Cx states.
6.4.1
Disabling Unused System Memory Outputs
Any system memory (SM) interface signal that goes to a memory module connector in
which it is not connected to any actual memory devices (such as DIMM connector is
unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM
signals are:
• Reduced power consumption.
• Reduced possible overshoot/undershoot signal quality issues seen by the processor
I/O buffer receivers caused by reflections from potentially un-terminated
transmission lines.
When a given rank is not populated, the corresponding chip select and CKE signals are
not driven.
At reset, all rows must be assumed to be populated, until it can be proven that they are
not populated. This is due to the fact that when CKE is tristated with an SO-DIMM
present, the DIMM is not guaranteed to maintain data integrity.
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SCKE tri-state should be enabled by BIOS where appropriate, since at reset all rows
must be assumed to be populated.
6.4.2
DRAM Power Management and Initialization
The processor implements extensive support for power management on the SDRAM
interface. There are four SDRAM operations associated with the Clock Enable (CKE)
signals, which the SDRAM controller supports. The processor drives four CKE pins to
perform these operations.
6.4.2.1
Initialization Role of CKE
During power-up, CKE is the only input to the SDRAM that is recognized (other than the
DDR3 reset pin) once power is applied. It must be driven LOW by the DDR controller to
make sure the SDRAM components float DQ and DQS during power- up.
CKE signals remain LOW (while any reset is active) until the BIOS writes to a
configuration register. Using this method, CKE is guaranteed to remain inactive for
much longer than the specified 200 micro-seconds after power and clocks to SDRAM
devices are stable.
6.4.2.2
Conditional Self-Refresh
Intel Rapid Memory Power Management (Intel RMPM) conditionally places memory into
self-refresh in the package C3 and C6 low-power states. RMPM functionality depends
on graphics/display state (relevant only when internal graphics is being used), as well
as memory traffic patterns generated by other connected I/O devices.
When entering the Suspend-to-RAM (STR) state, the processor core flushes pending
cycles and then places all SDRAM ranks into self refresh. In STR, the CKE signals
remain LOW so the SDRAM devices perform self-refresh.
The target behavior is to enter self-refresh for the package C3 and C6 states as long as
there are no memory requests to service.
6.4.2.3
Dynamic Power Down Operation
Dynamic power-down of memory is employed during normal operation. Based on idle
conditions, a given memory rank may be powered down. The IMC implements
aggressive CKE control to dynamically put the DRAM devices in a power down state.The
processor core controller can be configured to put the devices in active power down
(CKE deassertion with open pages) or precharge power down (CKE deassertion with all
pages closed). Precharge power down provides greater power savings but has a bigger
performance impact, since all pages will first be closed before putting the devices in
power down mode.
If dynamic power-down is enabled, all ranks are powered up before doing a refresh
cycle and all ranks are powered down at the end of refresh.
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6.4.2.4
DRAM I/O Power Management
Unused signals should be disabled to save power and reduce electromagnetic
interference. This includes all signals associated with an unused memory channel.
Clocks can be controlled on a per SO-DIMM basis. Exceptions are made for per SODIMM control signals such as CS#, CKE, and ODT for unpopulated SO-DIMM slots.
The I/O buffer for an unused signal should be tri-stated (output driver disabled), the
input receiver (differential sense-amp) should be disabled, and any DLL circuitry
related ONLY to unused signals should be disabled. The input path must be gated to
prevent spurious results due to noise on the unused signals (typically handled
automatically when input receiver is disabled).
6.5
PCI Express* (PCIe*) Power Management
• Active power management support using L0s, and L1 states.
• All inputs and outputs disabled in L3 Ready state.
§
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Power Up and Reset Sequence
7
Power Up and Reset Sequence
This chapter provides information on the following topics:
• “Power Up Sequences”
• “Power Down Sequences”
• “Reset Behavior”
7.1
SoC System States
7.1.1
System Sleeping States Control (S-states)
The SoC supports the S0, S3, S4, and S5 sleep states. S4 and S5 states are identical
from a hardware and power perspective. The differentiation is software determined (S4
= Suspend to Disk).
The SoC platform architecture assumes the usage of an external power management
controller e.g., CPLD or PMIC. Some flows in this section refer to the power
management controller for support of the S-states transitions.
The SoC sleep states are described in Chapter 6, “Power Management”.
7.2
Power Up Sequences
7.2.1
RTC Power Well Transition (G5 to G3 States Transition)
When RTC_VCC (Real Time Clock power) is applied via RTC battery, the following
occurs (see Figure 12 for timing):
1. RTC_VCC ramps. ILB_RTC_TEST# should be low.
2. The system starts the real time clock oscillator.
3. A minimum of t1 units after RTC_VCC ramps, the external RTC RC circuit de-asserts
ILB_RTC_TEST# and ILB_RTC_RTC#. The system is now in the G3 state. RTC
oscillator is unlikely to be stable at this point.
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Figure 12. RTC Power Well Timing Diagrams
G3
RTC_VCC
t1
•
ILB_RTC_TES
T# &
ILB_RTC_RTC
#
Osc Startup
ILB_RTC_CLK
Table 58.
Clock Valid
RTC Power Well Timing Parameters
Parameter
t1
Description
Min
Max
Units
9
-
ms
RTC_VCC to ILB_RTC_TEST# and
ILB_RTC_RTC# de-assertion
NOTES:
1.
2.
7.2.2
This delay is typically created from an RC circuit.
The oscillator startup times are component and design specific. A crystal oscillator can take several
second to reach a large enough voltage swing. A silicon oscillator can have startups times
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